Add power I2C support for PXA3xx processors Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
		
			
				
	
	
		
			82 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			82 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  *  i2c_pxa.h
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|  *
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|  *  Copyright (C) 2002 Intrinsyc Software Inc.
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|  *
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|  *  This program is free software; you can redistribute it and/or modify
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|  *  it under the terms of the GNU General Public License version 2 as
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|  *  published by the Free Software Foundation.
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|  *
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|  */
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| #ifndef _I2C_PXA_H_
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| #define _I2C_PXA_H_
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| 
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| #if 0
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| #define DEF_TIMEOUT             3
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| #else
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| /* need a longer timeout if we're dealing with the fact we may well be
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|  * looking at a multi-master environment
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| */
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| #define DEF_TIMEOUT             32
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| #endif
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| 
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| #define BUS_ERROR               (-EREMOTEIO)
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| #define XFER_NAKED              (-ECONNREFUSED)
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| #define I2C_RETRY               (-2000) /* an error has occurred retry transmit */
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| 
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| /* ICR initialize bit values
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| *
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| *  15. FM       0 (100 Khz operation)
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| *  14. UR       0 (No unit reset)
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| *  13. SADIE    0 (Disables the unit from interrupting on slave addresses
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| *                                       matching its slave address)
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| *  12. ALDIE    0 (Disables the unit from interrupt when it loses arbitration
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| *                                       in master mode)
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| *  11. SSDIE    0 (Disables interrupts from a slave stop detected, in slave mode)
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| *  10. BEIE     1 (Enable interrupts from detected bus errors, no ACK sent)
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| *  9.  IRFIE    1 (Enable interrupts from full buffer received)
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| *  8.  ITEIE    1 (Enables the I2C unit to interrupt when transmit buffer empty)
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| *  7.  GCD      1 (Disables i2c unit response to general call messages as a slave)
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| *  6.  IUE      0 (Disable unit until we change settings)
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| *  5.  SCLE     1 (Enables the i2c clock output for master mode (drives SCL)
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| *  4.  MA       0 (Only send stop with the ICR stop bit)
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| *  3.  TB       0 (We are not transmitting a byte initially)
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| *  2.  ACKNAK   0 (Send an ACK after the unit receives a byte)
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| *  1.  STOP     0 (Do not send a STOP)
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| *  0.  START    0 (Do not send a START)
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| *
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| */
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| #define I2C_ICR_INIT	(ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
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| 
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| /* I2C status register init values
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|  *
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|  * 10. BED      1 (Clear bus error detected)
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|  * 9.  SAD      1 (Clear slave address detected)
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|  * 7.  IRF      1 (Clear IDBR Receive Full)
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|  * 6.  ITE      1 (Clear IDBR Transmit Empty)
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|  * 5.  ALD      1 (Clear Arbitration Loss Detected)
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|  * 4.  SSD      1 (Clear Slave Stop Detected)
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|  */
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| #define I2C_ISR_INIT	0x7FF  /* status register init */
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| 
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| struct i2c_slave_client;
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| 
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| struct i2c_pxa_platform_data {
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| 	unsigned int		slave_addr;
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| 	struct i2c_slave_client	*slave;
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| 	unsigned int		class;
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| 	int			use_pio;
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| };
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| 
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| extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
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| 
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| #ifdef CONFIG_PXA27x
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| extern void pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info);
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| #endif
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| 
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| #ifdef CONFIG_PXA3xx
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| extern void pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info);
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| #endif
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| 
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| #endif
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