linux/arch/ia64/mm
Bjorn Helgaas 9b50ffb0c0 [IA64] make ioremap avoid unsupported attributes
Example memory map (from HP sx1000 with VGA enabled):
    0x00000 - 0x9FFFF supports only WB (cacheable) access
    0xA0000 - 0xBFFFF supports only UC (uncacheable) access
    0xC0000 - 0xFFFFF supports only WB (cacheable) access

pci_read_rom() indirectly uses ioremap(0xC0000) to read the shadow VGA option
ROM.  ioremap() used to default to a 16MB or 64MB UC kernel identity mapping,
which would cause an MCA when reading 0xC0000 since only WB is supported there.

X uses reads the option ROM to initialize devices.  A smaller test case is:
  # echo 1 > /sys/bus/pci/devices/0000:aa:03.0/rom
  # cp /sys/bus/pci/devices/0000:aa:03.0/rom x

To avoid this, we can use the same ioremap_page_range() strategy that most
architectures use for all ioremaps.  These page table mappings come out of the
vmalloc area.  On ia64, these are in region 5 (0xA... addresses) and typically
use 16KB or 64KB mappings instead of 16MB or 64MB mappings.  The smaller
mappings give more flexibility to use the correct attributes.

Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2007-03-30 09:37:41 -07:00
..
contig.c [IA64] min_low_pfn and max_low_pfn calculation fix 2007-03-20 13:41:57 -07:00
discontig.c [IA64] min_low_pfn and max_low_pfn calculation fix 2007-03-20 13:41:57 -07:00
extable.c Remove obsolete #include <linux/config.h> 2006-06-30 19:25:36 +02:00
fault.c [PATCH] pidspace: is_init() 2006-09-29 09:18:12 -07:00
hugetlbpage.c [PATCH] shared page table for hugetlb page 2006-12-07 08:39:21 -08:00
init.c [IA64] bugfix stack layout upside-down 2007-03-29 15:15:24 -07:00
ioremap.c [IA64] make ioremap avoid unsupported attributes 2007-03-30 09:37:41 -07:00
Makefile [PATCH] ia64: ioremap: check EFI for valid memory attributes 2006-03-26 08:56:54 -08:00
numa.c [PATCH] hot-add-mem x86_64: memory_add_physaddr_to_nid node fixup 2006-10-01 00:39:18 -07:00
tlb.c Remove obsolete #include <linux/config.h> 2006-06-30 19:25:36 +02:00