forked from Minki/linux
fe56b9e6a8
The Qlogic Everest Driver is the backend module for the QL4xxx ethernet
products by Qlogic.
This module serves two main purposes:
1. It's responsible to contain all the common code that will be shared
between the various drivers that would be used with said line of
products. Flows such as chip initialization and de-initialization
fall under this category.
2. It would abstract the protocol-specific HW & FW components, allowing
the protocol drivers to have a clean APIs which is detached in its
slowpath configuration from the actual HSI.
This adds a very basic module without any protocol-specific bits.
I.e., this adds a basic implementation that almost entirely falls under
the first category.
Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: Ariel Elior <Ariel.Elior@qlogic.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
392 lines
9.3 KiB
C
392 lines
9.3 KiB
C
/* QLogic qed NIC Driver
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#ifndef _QED_INT_H
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#define _QED_INT_H
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#include <linux/types.h>
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#include <linux/slab.h>
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#include "qed.h"
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/* Fields of IGU PF CONFIGRATION REGISTER */
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#define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */
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#define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */
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#define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */
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#define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */
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#define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */
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#define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */
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/* Igu control commands
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*/
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enum igu_ctrl_cmd {
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IGU_CTRL_CMD_TYPE_RD,
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IGU_CTRL_CMD_TYPE_WR,
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MAX_IGU_CTRL_CMD
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};
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/* Control register for the IGU command register
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*/
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struct igu_ctrl_reg {
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u32 ctrl_data;
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#define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */
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#define IGU_CTRL_REG_FID_SHIFT 0
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#define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */
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#define IGU_CTRL_REG_PXP_ADDR_SHIFT 16
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#define IGU_CTRL_REG_RESERVED_MASK 0x1
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#define IGU_CTRL_REG_RESERVED_SHIFT 28
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#define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */
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#define IGU_CTRL_REG_TYPE_SHIFT 31
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};
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enum qed_coalescing_fsm {
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QED_COAL_RX_STATE_MACHINE,
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QED_COAL_TX_STATE_MACHINE
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};
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/**
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* @brief qed_int_cau_conf_pi - configure cau for a given
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* status block
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*
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* @param p_hwfn
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* @param p_ptt
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* @param igu_sb_id
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* @param pi_index
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* @param state
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* @param timeset
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*/
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void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u16 igu_sb_id,
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u32 pi_index,
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enum qed_coalescing_fsm coalescing_fsm,
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u8 timeset);
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/**
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* @brief qed_int_igu_enable_int - enable device interrupts
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*
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* @param p_hwfn
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* @param p_ptt
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* @param int_mode - interrupt mode to use
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*/
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void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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enum qed_int_mode int_mode);
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/**
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* @brief qed_int_igu_disable_int - disable device interrupts
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*
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* @param p_hwfn
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* @param p_ptt
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*/
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void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt);
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/**
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* @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc
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* register from igu.
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*
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* @param p_hwfn
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*
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* @return u64
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*/
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u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn);
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#define QED_SP_SB_ID 0xffff
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/**
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* @brief qed_int_sb_init - Initializes the sb_info structure.
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*
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* once the structure is initialized it can be passed to sb related functions.
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*
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* @param p_hwfn
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* @param p_ptt
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* @param sb_info points to an uninitialized (but
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* allocated) sb_info structure
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* @param sb_virt_addr
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* @param sb_phy_addr
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* @param sb_id the sb_id to be used (zero based in driver)
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* should use QED_SP_SB_ID for SP Status block
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*
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* @return int
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*/
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int qed_int_sb_init(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct qed_sb_info *sb_info,
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void *sb_virt_addr,
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dma_addr_t sb_phy_addr,
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u16 sb_id);
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/**
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* @brief qed_int_sb_setup - Setup the sb.
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*
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* @param p_hwfn
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* @param p_ptt
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* @param sb_info initialized sb_info structure
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*/
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void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct qed_sb_info *sb_info);
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/**
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* @brief qed_int_sb_release - releases the sb_info structure.
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*
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* once the structure is released, it's memory can be freed
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*
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* @param p_hwfn
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* @param sb_info points to an allocated sb_info structure
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* @param sb_id the sb_id to be used (zero based in driver)
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* should never be equal to QED_SP_SB_ID
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* (SP Status block)
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*
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* @return int
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*/
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int qed_int_sb_release(struct qed_hwfn *p_hwfn,
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struct qed_sb_info *sb_info,
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u16 sb_id);
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/**
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* @brief qed_int_sp_dpc - To be called when an interrupt is received on the
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* default status block.
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*
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* @param p_hwfn - pointer to hwfn
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*
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*/
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void qed_int_sp_dpc(unsigned long hwfn_cookie);
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/**
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* @brief qed_int_get_num_sbs - get the number of status
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* blocks configured for this funciton in the igu.
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*
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* @param p_hwfn
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* @param p_iov_blks - configured free blks for vfs
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*
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* @return int - number of status blocks configured
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*/
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int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
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int *p_iov_blks);
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/**
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* @file
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*
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* @brief Interrupt handler
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*/
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#define QED_CAU_DEF_RX_TIMER_RES 0
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#define QED_CAU_DEF_TX_TIMER_RES 0
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#define QED_SB_ATT_IDX 0x0001
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#define QED_SB_EVENT_MASK 0x0003
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#define SB_ALIGNED_SIZE(p_hwfn) \
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ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)
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struct qed_igu_block {
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u8 status;
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#define QED_IGU_STATUS_FREE 0x01
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#define QED_IGU_STATUS_VALID 0x02
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#define QED_IGU_STATUS_PF 0x04
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u8 vector_number;
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u8 function_id;
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u8 is_pf;
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};
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struct qed_igu_map {
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struct qed_igu_block igu_blocks[MAX_TOT_SB_PER_PATH];
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};
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struct qed_igu_info {
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struct qed_igu_map igu_map;
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u16 igu_dsb_id;
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u16 igu_base_sb;
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u16 igu_base_sb_iov;
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u16 igu_sb_cnt;
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u16 igu_sb_cnt_iov;
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u16 free_blks;
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};
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/* TODO Names of function may change... */
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void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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bool b_set,
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bool b_slowpath);
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void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn);
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/**
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* @brief qed_int_igu_read_cam - Reads the IGU CAM.
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* This function needs to be called during hardware
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* prepare. It reads the info from igu cam to know which
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* status block is the default / base status block etc.
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*
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* @param p_hwfn
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* @param p_ptt
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*
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* @return int
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*/
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int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt);
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typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn,
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void *cookie);
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/**
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* @brief qed_int_register_cb - Register callback func for
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* slowhwfn statusblock.
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*
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* Every protocol that uses the slowhwfn status block
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* should register a callback function that will be called
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* once there is an update of the sp status block.
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*
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* @param p_hwfn
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* @param comp_cb - function to be called when there is an
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* interrupt on the sp sb
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*
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* @param cookie - passed to the callback function
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* @param sb_idx - OUT parameter which gives the chosen index
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* for this protocol.
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* @param p_fw_cons - pointer to the actual address of the
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* consumer for this protocol.
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*
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* @return int
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*/
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int qed_int_register_cb(struct qed_hwfn *p_hwfn,
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qed_int_comp_cb_t comp_cb,
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void *cookie,
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u8 *sb_idx,
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__le16 **p_fw_cons);
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/**
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* @brief qed_int_unregister_cb - Unregisters callback
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* function from sp sb.
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* Partner of qed_int_register_cb -> should be called
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* when no longer required.
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*
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* @param p_hwfn
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* @param pi
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*
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* @return int
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*/
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int qed_int_unregister_cb(struct qed_hwfn *p_hwfn,
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u8 pi);
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/**
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* @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id.
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*
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* @param p_hwfn
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*
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* @return u16
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*/
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u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn);
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/**
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* @brief Status block cleanup. Should be called for each status
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* block that will be used -> both PF / VF
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*
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* @param p_hwfn
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* @param p_ptt
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* @param sb_id - igu status block id
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* @param cleanup_set - set(1) / clear(0)
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* @param opaque_fid - the function for which to perform
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* cleanup, for example a PF on behalf of
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* its VFs.
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*/
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void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 sb_id,
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bool cleanup_set,
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u16 opaque_fid);
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/**
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* @brief Status block cleanup. Should be called for each status
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* block that will be used -> both PF / VF
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*
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* @param p_hwfn
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* @param p_ptt
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* @param sb_id - igu status block id
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* @param opaque - opaque fid of the sb owner.
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* @param cleanup_set - set(1) / clear(0)
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*/
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void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 sb_id,
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u16 opaque,
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bool b_set);
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/**
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* @brief qed_int_cau_conf - configure cau for a given status
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* block
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*
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* @param p_hwfn
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* @param ptt
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* @param sb_phys
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* @param igu_sb_id
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* @param vf_number
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* @param vf_valid
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*/
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void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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dma_addr_t sb_phys,
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u16 igu_sb_id,
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u16 vf_number,
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u8 vf_valid);
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/**
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* @brief qed_int_alloc
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*
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* @param p_hwfn
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* @param p_ptt
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*
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* @return int
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*/
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int qed_int_alloc(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt);
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/**
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* @brief qed_int_free
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*
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* @param p_hwfn
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*/
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void qed_int_free(struct qed_hwfn *p_hwfn);
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/**
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* @brief qed_int_setup
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*
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* @param p_hwfn
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* @param p_ptt
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*/
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void qed_int_setup(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt);
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/**
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* @brief - Enable Interrupt & Attention for hw function
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*
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* @param p_hwfn
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* @param p_ptt
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* @param int_mode
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*/
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void qed_int_igu_enable(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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enum qed_int_mode int_mode);
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/**
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* @brief - Initialize CAU status block entry
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*
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* @param p_hwfn
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* @param p_sb_entry
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* @param pf_id
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* @param vf_number
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* @param vf_valid
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*/
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void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
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struct cau_sb_entry *p_sb_entry,
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u8 pf_id,
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u16 vf_number,
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u8 vf_valid);
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#define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev))
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#endif
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