forked from Minki/linux
8a9fd83230
Move CoreSight headers to the SPDX identifier. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1524089118-27595-1-git-send-email-mathieu.poirier@linaro.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright(C) 2015 Linaro Limited. All rights reserved.
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* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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*/
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#include <stdbool.h>
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#include <linux/coresight-pmu.h>
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#include "../../util/auxtrace.h"
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#include "../../util/evlist.h"
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#include "../../util/pmu.h"
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#include "cs-etm.h"
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#include "arm-spe.h"
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static struct perf_pmu **find_all_arm_spe_pmus(int *nr_spes, int *err)
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{
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struct perf_pmu **arm_spe_pmus = NULL;
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int ret, i, nr_cpus = sysconf(_SC_NPROCESSORS_CONF);
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/* arm_spe_xxxxxxxxx\0 */
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char arm_spe_pmu_name[sizeof(ARM_SPE_PMU_NAME) + 10];
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arm_spe_pmus = zalloc(sizeof(struct perf_pmu *) * nr_cpus);
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if (!arm_spe_pmus) {
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pr_err("spes alloc failed\n");
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*err = -ENOMEM;
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return NULL;
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}
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for (i = 0; i < nr_cpus; i++) {
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ret = sprintf(arm_spe_pmu_name, "%s%d", ARM_SPE_PMU_NAME, i);
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if (ret < 0) {
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pr_err("sprintf failed\n");
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*err = -ENOMEM;
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return NULL;
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}
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arm_spe_pmus[*nr_spes] = perf_pmu__find(arm_spe_pmu_name);
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if (arm_spe_pmus[*nr_spes]) {
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pr_debug2("%s %d: arm_spe_pmu %d type %d name %s\n",
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__func__, __LINE__, *nr_spes,
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arm_spe_pmus[*nr_spes]->type,
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arm_spe_pmus[*nr_spes]->name);
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(*nr_spes)++;
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}
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}
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return arm_spe_pmus;
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}
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struct auxtrace_record
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*auxtrace_record__init(struct perf_evlist *evlist, int *err)
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{
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struct perf_pmu *cs_etm_pmu;
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struct perf_evsel *evsel;
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bool found_etm = false;
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bool found_spe = false;
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static struct perf_pmu **arm_spe_pmus = NULL;
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static int nr_spes = 0;
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int i = 0;
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if (!evlist)
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return NULL;
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cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME);
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if (!arm_spe_pmus)
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arm_spe_pmus = find_all_arm_spe_pmus(&nr_spes, err);
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evlist__for_each_entry(evlist, evsel) {
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if (cs_etm_pmu &&
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evsel->attr.type == cs_etm_pmu->type)
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found_etm = true;
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if (!nr_spes)
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continue;
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for (i = 0; i < nr_spes; i++) {
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if (evsel->attr.type == arm_spe_pmus[i]->type) {
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found_spe = true;
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break;
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}
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}
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}
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if (found_etm && found_spe) {
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pr_err("Concurrent ARM Coresight ETM and SPE operation not currently supported\n");
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*err = -EOPNOTSUPP;
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return NULL;
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}
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if (found_etm)
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return cs_etm_record_init(err);
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#if defined(__aarch64__)
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if (found_spe)
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return arm_spe_recording_init(err, arm_spe_pmus[i]);
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#endif
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/*
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* Clear 'err' even if we haven't found an event - that way perf
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* record can still be used even if tracers aren't present. The NULL
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* return value will take care of telling the infrastructure HW tracing
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* isn't available.
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*/
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*err = 0;
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return NULL;
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}
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