9021c317b7
This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS). Some of its capabilities include: * 4K@60fps; * HDR10; * one graphics and 2 video pipelines; * on-the-fly decompression of compressed video and graphics; The reference manual can be found here: https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM The current patch adds only basic functionality: one primary plane for graphics, linear, tiled and super-tiled buffers support (no graphics decompression yet), no HDR10 and no video planes. Video planes support and HDR10 will be added in subsequent patches once per-plane de-gamma/CSC/gamma support is in. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/20200731081836.3048-3-laurentiu.palcu@oss.nxp.com
71 lines
1.5 KiB
C
71 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP.
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*/
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include "dcss-dev.h"
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#define DCSS_BLKCTL_RESET_CTRL 0x00
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#define B_CLK_RESETN BIT(0)
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#define APB_CLK_RESETN BIT(1)
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#define P_CLK_RESETN BIT(2)
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#define RTR_CLK_RESETN BIT(4)
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#define DCSS_BLKCTL_CONTROL0 0x10
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#define HDMI_MIPI_CLK_SEL BIT(0)
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#define DISPMIX_REFCLK_SEL_POS 4
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#define DISPMIX_REFCLK_SEL_MASK GENMASK(5, 4)
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#define DISPMIX_PIXCLK_SEL BIT(8)
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#define HDMI_SRC_SECURE_EN BIT(16)
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struct dcss_blkctl {
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struct dcss_dev *dcss;
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void __iomem *base_reg;
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};
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void dcss_blkctl_cfg(struct dcss_blkctl *blkctl)
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{
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if (blkctl->dcss->hdmi_output)
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dcss_writel(0, blkctl->base_reg + DCSS_BLKCTL_CONTROL0);
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else
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dcss_writel(DISPMIX_PIXCLK_SEL,
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blkctl->base_reg + DCSS_BLKCTL_CONTROL0);
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dcss_set(B_CLK_RESETN | APB_CLK_RESETN | P_CLK_RESETN | RTR_CLK_RESETN,
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blkctl->base_reg + DCSS_BLKCTL_RESET_CTRL);
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}
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int dcss_blkctl_init(struct dcss_dev *dcss, unsigned long blkctl_base)
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{
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struct dcss_blkctl *blkctl;
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blkctl = kzalloc(sizeof(*blkctl), GFP_KERNEL);
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if (!blkctl)
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return -ENOMEM;
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blkctl->base_reg = ioremap(blkctl_base, SZ_4K);
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if (!blkctl->base_reg) {
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dev_err(dcss->dev, "unable to remap BLK CTRL base\n");
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kfree(blkctl);
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return -ENOMEM;
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}
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dcss->blkctl = blkctl;
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blkctl->dcss = dcss;
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dcss_blkctl_cfg(blkctl);
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return 0;
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}
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void dcss_blkctl_exit(struct dcss_blkctl *blkctl)
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{
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if (blkctl->base_reg)
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iounmap(blkctl->base_reg);
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kfree(blkctl);
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}
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