linux/drivers/pinctrl/qcom
Stephen Boyd b55326dc96 pinctrl: msm: Really mask level interrupts to prevent latching
The interrupt controller hardware in this pin controller has two status
enable bits. The first "normal" status enable bit enables or disables
the summary interrupt line being raised when a gpio interrupt triggers
and the "raw" status enable bit allows or prevents the hardware from
latching an interrupt into the status register for a gpio interrupt.
Currently we just toggle the "normal" status enable bit in the mask and
unmask ops so that the summary irq interrupt going to the CPU's
interrupt controller doesn't trigger for the masked gpio interrupt.

For a level triggered interrupt, the flow would be as follows: the pin
controller sees the interrupt, latches the status into the status
register, raises the summary irq to the CPU, summary irq handler runs
and calls handle_level_irq(), handle_level_irq() masks and acks the gpio
interrupt, the interrupt handler runs, and finally unmask the interrupt.
When the interrupt handler completes, we expect that the interrupt line
level will go back to the deasserted state so the genirq code can unmask
the interrupt without it triggering again.

If we only mask the interrupt by clearing the "normal" status enable bit
then we'll ack the interrupt but it will continue to show up as pending
in the status register because the raw status bit is enabled, the
hardware hasn't deasserted the line, and thus the asserted state latches
into the status register again. When the hardware deasserts the
interrupt the pin controller still thinks there is a pending unserviced
level interrupt because it latched it earlier. This behavior causes
software to see an extra interrupt for level type interrupts each time
the interrupt is handled.

Let's fix this by clearing the raw status enable bit for level type
interrupts so that the hardware stops latching the status of the
interrupt after we ack it. We don't do this for edge type interrupts
because it seems that toggling the raw status enable bit for edge type
interrupts causes spurious edge interrupts.

Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 09:38:50 +02:00
..
Kconfig pinctrl: qcom: Add sdm845 pinctrl driver 2018-02-12 10:47:23 +01:00
Makefile pinctrl: qcom: Add sdm845 pinctrl driver 2018-02-12 10:47:23 +01:00
pinctrl-apq8064.c pinctrl: qcom: General Purpose clocks for apq8064 2017-08-31 11:32:19 +02:00
pinctrl-apq8084.c
pinctrl-ipq4019.c pinctrl: msm: add support to configure ipq40xx GPIO_PULL bits 2017-08-14 15:00:59 +02:00
pinctrl-ipq8064.c
pinctrl-ipq8074.c pinctrl: qcom: Add ipq8074 pinctrl driver 2017-06-29 15:12:40 +02:00
pinctrl-mdm9615.c
pinctrl-msm8x74.c
pinctrl-msm8660.c pinctrl: qcom: msm8660: rename some SDC1->SDC4 2017-01-03 09:26:20 +01:00
pinctrl-msm8916.c
pinctrl-msm8960.c
pinctrl-msm8994.c pinctrl: qcom: Add msm8994 pinctrl driver 2016-11-04 23:55:36 +01:00
pinctrl-msm8996.c
pinctrl-msm8998.c pinctrl: msm8998: Remove owner assignment from platform_driver 2018-03-27 14:05:11 +02:00
pinctrl-msm.c pinctrl: msm: Really mask level interrupts to prevent latching 2018-08-29 09:38:50 +02:00
pinctrl-msm.h pinctrl: msm: add support to configure ipq40xx GPIO_PULL bits 2017-08-14 15:00:59 +02:00
pinctrl-qdf2xxx.c pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002 2018-05-02 14:36:08 +02:00
pinctrl-sdm845.c pinctrl: qcom: Add sdm845 pinctrl driver 2018-02-12 10:47:23 +01:00
pinctrl-spmi-gpio.c pinctrl: qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliant 2018-07-09 13:16:01 +02:00
pinctrl-spmi-mpp.c
pinctrl-ssbi-gpio.c pinctrl: qcom: ssbi-gpio: constify gpio_chip structure 2017-08-14 15:00:59 +02:00
pinctrl-ssbi-mpp.c pinctrl: qcom: ssbi: mpp: constify gpio_chip structure 2017-08-14 15:01:01 +02:00