forked from Minki/linux
d4db4e5532
There are three SoC families newly dded to the 32-bit and 64-bit Arm architecture code in the kernel this time: - Daniel Palmer adds initial support for two chips made by MStar, a taiwanese SoC manufacturer that became part of Mediatek in 2012. For now, the added support is fairly minimal, with just two of its Cortex-A7 based 32-bit camera chips getting support for a limited set of on-chip peripherals. - Lars Povlsen from Microchip adds support for their new Sparx5 family of ethernet switch chips using 64-bit Cortex-A53 cores. These are descended from earlier VSC7xxx SparX and Ocelot chips using 32-bit MIPS cores. - Daniele Alessandrelli from Intel adds support for the new Keem Bay SoC for computer vision, built around a Movidius VPU with Linux running on Arm Cortex-A53 cores. Signed-off-by: Arnd Bergmann <arnd@arndb.de> -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAl8j31MACgkQmmx57+YA GNnS7Q//achCOtBeIblV8Fyfp/lTYNpT9hFTQ5cGaoyjl9Lm1rcVCISCEGqIEJAV FRQBz3YcQWA9pIWIf79oh6QphcoW/wUTCE+cjnHP+EOkqvw9aGFBm4nOUt4Gz92a +gGs9HqcrxB+3ysQEDGugwRrE6htrOoCnWyurh5zZNvAEry+MV6LBwfxSUrLKy8b iwnwl/KvWI47mWAj5nJ7fbXAgxRjFdEz+mvNBjqKhJ/OELsnWRXcxmJxF651DEb6 e/ydD7OtrWI1+81/yQxS7SeDlatFHE0JvP4WZHBGm6TB7Z3pdqIZI598UN0lVvbR jvtljiAa2UA7h6NjscD6ECWktrF8LO8i/8ref7Fr3za/FKiLTYP2BQymnlk5nLAj RuCvR8oriqBbseZlkGrs4afjpfwurUKNhhjVse/M3ORYYK++Bra6GZWL4gnlA2wB GbFZ6MAw2bnbKrO6rRTu+F1NFq5/l71LP1r3Li3xbyfZ7I/XJ5aiE6knQ+vtk6Np pfvCYSILOSnulYZvdaL/W4HV98mzjHSE4eUegGDTMKNv2dVNRGI3Mnnur7+kSXLu 550qg+GXv8JkQlkFkT2BsuaiPULOUKHFtK42fo2XhQL/zoaFlBU7HehtSBdtcKPy XIlEEk32q+QyABKav2QJnGJMcWzfq2SSmsUliVU72zD38dG/0Fw= =Yy3D -----END PGP SIGNATURE----- Merge tag 'arm-newsoc-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull new ARM SoC support from Arnd Bergmann: "There are three SoC families newly dded to the 32-bit and 64-bit Arm architecture code in the kernel this time: - Daniel Palmer adds initial support for two chips made by MStar, a taiwanese SoC manufacturer that became part of Mediatek in 2012. For now, the added support is fairly minimal, with just two of its Cortex-A7 based 32-bit camera chips getting support for a limited set of on-chip peripherals. - Lars Povlsen from Microchip adds support for their new Sparx5 family of ethernet switch chips using 64-bit Cortex-A53 cores. These are descended from earlier VSC7xxx SparX and Ocelot chips using 32-bit MIPS cores. - Daniele Alessandrelli from Intel adds support for the new Keem Bay SoC for computer vision, built around a Movidius VPU with Linux running on Arm Cortex-A53 cores" * tag 'arm-newsoc-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits) ARM: mstar: Correct the compatible string for pmsleep dt-bindings: arm: mstar: remove the binding description for mstar,pmsleep dt-bindings: mfd: syscon: add compatible string for mstar,msc313-pmsleep ARM: mstar: Add reboot support ARM: mstar: Add "pmsleep" node to base dtsi ARM: mstar: Add PMU ARM: mstar: Adjust IMI size for infinity3 ARM: mstar: Adjust IMI size for mercury5 ARM: mstar: Adjust IMI size of infinity ARM: mstar: Add IMI SRAM region dt-bindings: arm: mstar: Move existing MStar binding descriptions dt-bindings: arm: mstar: Add binding details for mstar, pmsleep ARM: mstar: Fix dts filename for 70mai midrive d08 ARM: mstar: Add dts for 70mai midrive d08 ARM: mstar: Add dts for msc313(e) based BreadBee boards ARM: mstar: Add mercury5 series dtsis ARM: mstar: Add infinity/infinity3 family dtsis ARM: mstar: Add Armv7 base dtsi ARM: mstar: Add binding details for mstar,l3bridge ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCs ...
323 lines
7.5 KiB
Plaintext
323 lines
7.5 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
menu "Platform selection"
|
|
|
|
config ARCH_ACTIONS
|
|
bool "Actions Semi Platforms"
|
|
select OWL_TIMER
|
|
select PINCTRL
|
|
help
|
|
This enables support for the Actions Semiconductor S900 SoC family.
|
|
|
|
config ARCH_AGILEX
|
|
bool "Intel's Agilex SoCFPGA Family"
|
|
help
|
|
This enables support for Intel's Agilex SoCFPGA Family.
|
|
|
|
config ARCH_SUNXI
|
|
bool "Allwinner sunxi 64-bit SoC Family"
|
|
select ARCH_HAS_RESET_CONTROLLER
|
|
select GENERIC_IRQ_CHIP
|
|
select PINCTRL
|
|
select RESET_CONTROLLER
|
|
help
|
|
This enables support for Allwinner sunxi based SoCs like the A64.
|
|
|
|
config ARCH_ALPINE
|
|
bool "Annapurna Labs Alpine platform"
|
|
select ALPINE_MSI if PCI
|
|
help
|
|
This enables support for the Annapurna Labs Alpine
|
|
Soc family.
|
|
|
|
config ARCH_BCM2835
|
|
bool "Broadcom BCM2835 family"
|
|
select TIMER_OF
|
|
select GPIOLIB
|
|
select MFD_CORE
|
|
select PINCTRL
|
|
select PINCTRL_BCM2835
|
|
select ARM_AMBA
|
|
select ARM_GIC
|
|
select ARM_TIMER_SP804
|
|
help
|
|
This enables support for the Broadcom BCM2837 and BCM2711 SoC.
|
|
These SoCs are used in the Raspberry Pi 3 and 4 devices.
|
|
|
|
config ARCH_BCM_IPROC
|
|
bool "Broadcom iProc SoC Family"
|
|
select COMMON_CLK_IPROC
|
|
select GPIOLIB
|
|
select PINCTRL
|
|
help
|
|
This enables support for Broadcom iProc based SoCs
|
|
|
|
config ARCH_BERLIN
|
|
bool "Marvell Berlin SoC Family"
|
|
select DW_APB_ICTL
|
|
select GPIOLIB
|
|
select PINCTRL
|
|
help
|
|
This enables support for Marvell Berlin SoC Family
|
|
|
|
config ARCH_BITMAIN
|
|
bool "Bitmain SoC Platforms"
|
|
help
|
|
This enables support for the Bitmain SoC Family.
|
|
|
|
config ARCH_BRCMSTB
|
|
bool "Broadcom Set-Top-Box SoCs"
|
|
select ARCH_HAS_RESET_CONTROLLER
|
|
select BCM7038_L1_IRQ
|
|
select BRCMSTB_L2_IRQ
|
|
select GENERIC_IRQ_CHIP
|
|
select PINCTRL
|
|
help
|
|
This enables support for Broadcom's ARMv8 Set Top Box SoCs
|
|
|
|
config ARCH_EXYNOS
|
|
bool "ARMv8 based Samsung Exynos SoC family"
|
|
select COMMON_CLK_SAMSUNG
|
|
select EXYNOS_CHIPID
|
|
select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
|
|
select EXYNOS_PMU
|
|
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
|
select HAVE_S3C_RTC if RTC_CLASS
|
|
select PINCTRL
|
|
select PINCTRL_EXYNOS
|
|
select PM_GENERIC_DOMAINS if PM
|
|
select SOC_SAMSUNG
|
|
help
|
|
This enables support for ARMv8 based Samsung Exynos SoC family.
|
|
|
|
config ARCH_SPARX5
|
|
bool "ARMv8 based Microchip Sparx5 SoC family"
|
|
select PINCTRL
|
|
select DW_APB_TIMER_OF
|
|
help
|
|
This enables support for the Microchip Sparx5 ARMv8-based
|
|
SoC family of TSN-capable gigabit switches.
|
|
|
|
The SparX-5 Ethernet switch family provides a rich set of
|
|
switching features such as advanced TCAM-based VLAN and QoS
|
|
processing enabling delivery of differentiated services, and
|
|
security through TCAM-based frame processing using versatile
|
|
content aware processor (VCAP).
|
|
|
|
config ARCH_K3
|
|
bool "Texas Instruments Inc. K3 multicore SoC architecture"
|
|
select PM_GENERIC_DOMAINS if PM
|
|
select MAILBOX
|
|
select SOC_TI
|
|
select TI_MESSAGE_MANAGER
|
|
select TI_SCI_PROTOCOL
|
|
select TI_SCI_INTR_IRQCHIP
|
|
select TI_SCI_INTA_IRQCHIP
|
|
select TI_K3_SOCINFO
|
|
help
|
|
This enables support for Texas Instruments' K3 multicore SoC
|
|
architecture.
|
|
|
|
config ARCH_LAYERSCAPE
|
|
bool "ARMv8 based Freescale Layerscape SoC family"
|
|
select EDAC_SUPPORT
|
|
help
|
|
This enables support for the Freescale Layerscape SoC family.
|
|
|
|
config ARCH_LG1K
|
|
bool "LG Electronics LG1K SoC Family"
|
|
help
|
|
This enables support for LG Electronics LG1K SoC Family
|
|
|
|
config ARCH_HISI
|
|
bool "Hisilicon SoC Family"
|
|
select ARM_TIMER_SP804
|
|
select HISILICON_IRQ_MBIGEN if PCI
|
|
select PINCTRL
|
|
help
|
|
This enables support for Hisilicon ARMv8 SoC family
|
|
|
|
config ARCH_KEEMBAY
|
|
bool "Keem Bay SoC"
|
|
help
|
|
This enables support for Intel Movidius SoC code-named Keem Bay.
|
|
|
|
config ARCH_MEDIATEK
|
|
bool "MediaTek SoC Family"
|
|
select ARM_GIC
|
|
select PINCTRL
|
|
select MTK_TIMER
|
|
help
|
|
This enables support for MediaTek MT27xx, MT65xx, MT76xx
|
|
& MT81xx ARMv8 SoCs
|
|
|
|
config ARCH_MESON
|
|
bool "Amlogic Platforms"
|
|
select PINCTRL
|
|
select PINCTRL_MESON
|
|
select COMMON_CLK_GXBB
|
|
select COMMON_CLK_AXG
|
|
select COMMON_CLK_G12A
|
|
select MESON_IRQ_GPIO
|
|
help
|
|
This enables support for the arm64 based Amlogic SoCs
|
|
such as the s905, S905X/D, S912, A113X/D or S905X/D2
|
|
|
|
config ARCH_MVEBU
|
|
bool "Marvell EBU SoC Family"
|
|
select ARMADA_AP806_SYSCON
|
|
select ARMADA_CP110_SYSCON
|
|
select ARMADA_37XX_CLK
|
|
select GPIOLIB
|
|
select GPIOLIB_IRQCHIP
|
|
select MVEBU_GICP
|
|
select MVEBU_ICU
|
|
select MVEBU_ODMI
|
|
select MVEBU_PIC
|
|
select MVEBU_SEI
|
|
select OF_GPIO
|
|
select PINCTRL
|
|
select PINCTRL_ARMADA_37XX
|
|
select PINCTRL_ARMADA_AP806
|
|
select PINCTRL_ARMADA_CP110
|
|
help
|
|
This enables support for Marvell EBU familly, including:
|
|
- Armada 3700 SoC Family
|
|
- Armada 7K SoC Family
|
|
- Armada 8K SoC Family
|
|
|
|
config ARCH_MXC
|
|
bool "ARMv8 based NXP i.MX SoC family"
|
|
select ARM64_ERRATUM_843419
|
|
select ARM64_ERRATUM_845719 if COMPAT
|
|
select IMX_GPCV2
|
|
select IMX_GPCV2_PM_DOMAINS
|
|
select PM
|
|
select PM_GENERIC_DOMAINS
|
|
select SOC_BUS
|
|
select TIMER_IMX_SYS_CTR
|
|
help
|
|
This enables support for the ARMv8 based SoCs in the
|
|
NXP i.MX family.
|
|
|
|
config ARCH_QCOM
|
|
bool "Qualcomm Platforms"
|
|
select GPIOLIB
|
|
select PINCTRL
|
|
help
|
|
This enables support for the ARMv8 based Qualcomm chipsets.
|
|
|
|
config ARCH_REALTEK
|
|
bool "Realtek Platforms"
|
|
select RESET_CONTROLLER
|
|
help
|
|
This enables support for the ARMv8 based Realtek chipsets,
|
|
like the RTD1295.
|
|
|
|
config ARCH_RENESAS
|
|
bool "Renesas SoC Platforms"
|
|
select GPIOLIB
|
|
select PINCTRL
|
|
select SOC_BUS
|
|
help
|
|
This enables support for the ARMv8 based Renesas SoCs.
|
|
|
|
config ARCH_ROCKCHIP
|
|
bool "Rockchip Platforms"
|
|
select ARCH_HAS_RESET_CONTROLLER
|
|
select GPIOLIB
|
|
select PINCTRL
|
|
select PINCTRL_ROCKCHIP
|
|
select PM
|
|
select ROCKCHIP_TIMER
|
|
help
|
|
This enables support for the ARMv8 based Rockchip chipsets,
|
|
like the RK3368.
|
|
|
|
config ARCH_S32
|
|
bool "NXP S32 SoC Family"
|
|
help
|
|
This enables support for the NXP S32 family of processors.
|
|
|
|
config ARCH_SEATTLE
|
|
bool "AMD Seattle SoC Family"
|
|
help
|
|
This enables support for AMD Seattle SOC Family
|
|
|
|
config ARCH_STRATIX10
|
|
bool "Altera's Stratix 10 SoCFPGA Family"
|
|
help
|
|
This enables support for Altera's Stratix 10 SoCFPGA Family.
|
|
|
|
config ARCH_SYNQUACER
|
|
bool "Socionext SynQuacer SoC Family"
|
|
|
|
config ARCH_TEGRA
|
|
bool "NVIDIA Tegra SoC Family"
|
|
select ARCH_HAS_RESET_CONTROLLER
|
|
select ARM_GIC_PM
|
|
select CLKSRC_MMIO
|
|
select TIMER_OF
|
|
select GENERIC_CLOCKEVENTS
|
|
select GPIOLIB
|
|
select PINCTRL
|
|
select PM
|
|
select PM_GENERIC_DOMAINS
|
|
select RESET_CONTROLLER
|
|
help
|
|
This enables support for the NVIDIA Tegra SoC family.
|
|
|
|
config ARCH_SPRD
|
|
bool "Spreadtrum SoC platform"
|
|
help
|
|
Support for Spreadtrum ARM based SoCs
|
|
|
|
config ARCH_THUNDER
|
|
bool "Cavium Inc. Thunder SoC Family"
|
|
help
|
|
This enables support for Cavium's Thunder Family of SoCs.
|
|
|
|
config ARCH_THUNDER2
|
|
bool "Cavium ThunderX2 Server Processors"
|
|
select GPIOLIB
|
|
help
|
|
This enables support for Cavium's ThunderX2 CN99XX family of
|
|
server processors.
|
|
|
|
config ARCH_UNIPHIER
|
|
bool "Socionext UniPhier SoC Family"
|
|
select ARCH_HAS_RESET_CONTROLLER
|
|
select PINCTRL
|
|
select RESET_CONTROLLER
|
|
help
|
|
This enables support for Socionext UniPhier SoC family.
|
|
|
|
config ARCH_VEXPRESS
|
|
bool "ARMv8 software model (Versatile Express)"
|
|
select GPIOLIB
|
|
select PM
|
|
select PM_GENERIC_DOMAINS
|
|
help
|
|
This enables support for the ARMv8 software model (Versatile
|
|
Express).
|
|
|
|
config ARCH_VULCAN
|
|
def_bool n
|
|
|
|
config ARCH_XGENE
|
|
bool "AppliedMicro X-Gene SOC Family"
|
|
help
|
|
This enables support for AppliedMicro X-Gene SOC Family
|
|
|
|
config ARCH_ZX
|
|
bool "ZTE ZX SoC Family"
|
|
select PINCTRL
|
|
help
|
|
This enables support for ZTE ZX SoC Family
|
|
|
|
config ARCH_ZYNQMP
|
|
bool "Xilinx ZynqMP Family"
|
|
help
|
|
This enables support for Xilinx ZynqMP Family
|
|
|
|
endmenu
|