103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "channv04.h"
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#include "regsnv04.h"
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#include <core/client.h>
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#include <subdev/instmem.h>
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#include <nvif/class.h>
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#include <nvif/unpack.h>
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static int
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nv10_fifo_chan_ctor(struct nvkm_object *parent,
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struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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union {
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struct nv03_channel_dma_v0 v0;
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} *args = data;
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struct nv04_fifo *fifo = (void *)engine;
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struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;
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struct nv04_fifo_chan *chan;
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int ret;
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nvif_ioctl(parent, "create channel dma size %d\n", size);
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if (nvif_unpack(args->v0, 0, 0, false)) {
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nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
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"offset %08x\n", args->v0.version,
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args->v0.pushbuf, args->v0.offset);
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} else
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return ret;
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ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
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0x10000, args->v0.pushbuf,
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(1ULL << NVDEV_ENGINE_DMAOBJ) |
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(1ULL << NVDEV_ENGINE_SW) |
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(1ULL << NVDEV_ENGINE_GR), &chan);
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*pobject = nv_object(chan);
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if (ret)
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return ret;
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args->v0.chid = chan->base.chid;
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nv_parent(chan)->object_attach = nv04_fifo_object_attach;
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nv_parent(chan)->object_detach = nv04_fifo_object_detach;
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nv_parent(chan)->context_attach = nv04_fifo_context_attach;
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chan->ramfc = chan->base.chid * 32;
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nvkm_kmap(imem->ramfc);
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nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
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nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
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nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
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nvkm_wo32(imem->ramfc, chan->ramfc + 0x14,
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NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
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#ifdef __BIG_ENDIAN
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NV_PFIFO_CACHE1_BIG_ENDIAN |
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#endif
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NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
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nvkm_done(imem->ramfc);
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return 0;
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}
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static struct nvkm_ofuncs
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nv10_fifo_ofuncs = {
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.ctor = nv10_fifo_chan_ctor,
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.dtor = nv04_fifo_chan_dtor,
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.init = nv04_fifo_chan_init,
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.fini = nv04_fifo_chan_fini,
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.map = _nvkm_fifo_channel_map,
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.rd32 = _nvkm_fifo_channel_rd32,
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.wr32 = _nvkm_fifo_channel_wr32,
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.ntfy = _nvkm_fifo_channel_ntfy
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};
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struct nvkm_oclass
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nv10_fifo_sclass[] = {
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{ NV10_CHANNEL_DMA, &nv10_fifo_ofuncs },
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{}
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};
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