Charlene Liu 9983b80053 drm/amd/display: dp interlace MSA timing programming for Interlace mode. ... [Why] DP compliance box shows wrong MSA data. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-01-14 15:41:39 -05:00
..
acp	drm/amdgpu: Remove wrapper layer of cgs irq handling	2018-03-21 14:36:58 -05:00
amdgpu	drm/amdgpu: check if we need to reset at init time (v2)	2019-01-14 15:04:57 -05:00
amdkfd	drm/amdkfd: Don't assign dGPUs to APU topology devices	2019-01-14 15:37:33 -05:00
display	drm/amd/display: dp interlace MSA timing programming for Interlace mode.	2019-01-14 15:41:39 -05:00
include	drm/amdgpu: Add NBIO SMN headers v2	2019-01-14 15:04:53 -05:00
lib
powerplay	drm/amd/powerplay: run acg btc for Vega12	2019-01-14 15:37:43 -05:00