97fb5e8d9b
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
299 lines
8.5 KiB
C
299 lines
8.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*/
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#include "dpu_hwio.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_intf.h"
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#include "dpu_kms.h"
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#define INTF_TIMING_ENGINE_EN 0x000
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#define INTF_CONFIG 0x004
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#define INTF_HSYNC_CTL 0x008
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#define INTF_VSYNC_PERIOD_F0 0x00C
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#define INTF_VSYNC_PERIOD_F1 0x010
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#define INTF_VSYNC_PULSE_WIDTH_F0 0x014
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#define INTF_VSYNC_PULSE_WIDTH_F1 0x018
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#define INTF_DISPLAY_V_START_F0 0x01C
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#define INTF_DISPLAY_V_START_F1 0x020
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#define INTF_DISPLAY_V_END_F0 0x024
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#define INTF_DISPLAY_V_END_F1 0x028
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#define INTF_ACTIVE_V_START_F0 0x02C
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#define INTF_ACTIVE_V_START_F1 0x030
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#define INTF_ACTIVE_V_END_F0 0x034
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#define INTF_ACTIVE_V_END_F1 0x038
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#define INTF_DISPLAY_HCTL 0x03C
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#define INTF_ACTIVE_HCTL 0x040
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#define INTF_BORDER_COLOR 0x044
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#define INTF_UNDERFLOW_COLOR 0x048
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#define INTF_HSYNC_SKEW 0x04C
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#define INTF_POLARITY_CTL 0x050
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#define INTF_TEST_CTL 0x054
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#define INTF_TP_COLOR0 0x058
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#define INTF_TP_COLOR1 0x05C
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#define INTF_FRAME_LINE_COUNT_EN 0x0A8
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#define INTF_FRAME_COUNT 0x0AC
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#define INTF_LINE_COUNT 0x0B0
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#define INTF_DEFLICKER_CONFIG 0x0F0
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#define INTF_DEFLICKER_STRNG_COEFF 0x0F4
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#define INTF_DEFLICKER_WEAK_COEFF 0x0F8
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#define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084
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#define INTF_PANEL_FORMAT 0x090
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#define INTF_TPG_ENABLE 0x100
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#define INTF_TPG_MAIN_CONTROL 0x104
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#define INTF_TPG_VIDEO_CONFIG 0x108
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#define INTF_TPG_COMPONENT_LIMITS 0x10C
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#define INTF_TPG_RECTANGLE 0x110
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#define INTF_TPG_INITIAL_VALUE 0x114
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#define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118
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#define INTF_TPG_RGB_MAPPING 0x11C
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#define INTF_PROG_FETCH_START 0x170
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#define INTF_PROG_ROT_START 0x174
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#define INTF_FRAME_LINE_COUNT_EN 0x0A8
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#define INTF_FRAME_COUNT 0x0AC
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#define INTF_LINE_COUNT 0x0B0
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static struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
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struct dpu_mdss_cfg *m,
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void __iomem *addr,
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struct dpu_hw_blk_reg_map *b)
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{
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int i;
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for (i = 0; i < m->intf_count; i++) {
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if ((intf == m->intf[i].id) &&
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(m->intf[i].type != INTF_NONE)) {
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b->base_off = addr;
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b->blk_off = m->intf[i].base;
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b->length = m->intf[i].len;
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b->hwversion = m->hwversion;
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b->log_mask = DPU_DBG_MASK_INTF;
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return &m->intf[i];
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}
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}
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return ERR_PTR(-EINVAL);
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}
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static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
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const struct intf_timing_params *p,
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const struct dpu_format *fmt)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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u32 hsync_period, vsync_period;
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u32 display_v_start, display_v_end;
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u32 hsync_start_x, hsync_end_x;
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u32 active_h_start, active_h_end;
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u32 active_v_start, active_v_end;
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u32 active_hctl, display_hctl, hsync_ctl;
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u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;
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u32 panel_format;
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u32 intf_cfg;
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/* read interface_cfg */
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intf_cfg = DPU_REG_READ(c, INTF_CONFIG);
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hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
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p->h_front_porch;
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vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height +
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p->v_front_porch;
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display_v_start = ((p->vsync_pulse_width + p->v_back_porch) *
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hsync_period) + p->hsync_skew;
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display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
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p->hsync_skew - 1;
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if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
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display_v_start += p->hsync_pulse_width + p->h_back_porch;
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display_v_end -= p->h_front_porch;
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}
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hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
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hsync_end_x = hsync_period - p->h_front_porch - 1;
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if (p->width != p->xres) {
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active_h_start = hsync_start_x;
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active_h_end = active_h_start + p->xres - 1;
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} else {
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active_h_start = 0;
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active_h_end = 0;
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}
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if (p->height != p->yres) {
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active_v_start = display_v_start;
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active_v_end = active_v_start + (p->yres * hsync_period) - 1;
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} else {
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active_v_start = 0;
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active_v_end = 0;
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}
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if (active_h_end) {
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active_hctl = (active_h_end << 16) | active_h_start;
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intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */
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} else {
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active_hctl = 0;
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}
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if (active_v_end)
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intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */
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hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
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display_hctl = (hsync_end_x << 16) | hsync_start_x;
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den_polarity = 0;
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if (ctx->cap->type == INTF_HDMI) {
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hsync_polarity = p->yres >= 720 ? 0 : 1;
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vsync_polarity = p->yres >= 720 ? 0 : 1;
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} else {
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hsync_polarity = 0;
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vsync_polarity = 0;
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}
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polarity_ctl = (den_polarity << 2) | /* DEN Polarity */
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(vsync_polarity << 1) | /* VSYNC Polarity */
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(hsync_polarity << 0); /* HSYNC Polarity */
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if (!DPU_FORMAT_IS_YUV(fmt))
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panel_format = (fmt->bits[C0_G_Y] |
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(fmt->bits[C1_B_Cb] << 2) |
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(fmt->bits[C2_R_Cr] << 4) |
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(0x21 << 8));
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else
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/* Interface treats all the pixel data in RGB888 format */
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panel_format = (COLOR_8BIT |
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(COLOR_8BIT << 2) |
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(COLOR_8BIT << 4) |
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(0x21 << 8));
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DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
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DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);
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DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0,
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p->vsync_pulse_width * hsync_period);
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DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl);
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DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start);
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DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end);
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DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl);
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DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start);
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DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end);
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DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr);
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DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr);
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DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew);
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DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl);
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DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
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DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
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DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
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}
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static void dpu_hw_intf_enable_timing_engine(
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struct dpu_hw_intf *intf,
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u8 enable)
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{
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struct dpu_hw_blk_reg_map *c = &intf->hw;
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/* Note: Display interface select is handled in top block hw layer */
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DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0);
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}
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static void dpu_hw_intf_setup_prg_fetch(
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struct dpu_hw_intf *intf,
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const struct intf_prog_fetch *fetch)
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{
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struct dpu_hw_blk_reg_map *c = &intf->hw;
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int fetch_enable;
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/*
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* Fetch should always be outside the active lines. If the fetching
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* is programmed within active region, hardware behavior is unknown.
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*/
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fetch_enable = DPU_REG_READ(c, INTF_CONFIG);
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if (fetch->enable) {
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fetch_enable |= BIT(31);
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DPU_REG_WRITE(c, INTF_PROG_FETCH_START,
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fetch->fetch_start);
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} else {
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fetch_enable &= ~BIT(31);
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}
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DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable);
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}
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static void dpu_hw_intf_get_status(
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struct dpu_hw_intf *intf,
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struct intf_status *s)
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{
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struct dpu_hw_blk_reg_map *c = &intf->hw;
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s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
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if (s->is_en) {
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s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);
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s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT);
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} else {
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s->line_count = 0;
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s->frame_count = 0;
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}
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}
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static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
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{
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struct dpu_hw_blk_reg_map *c;
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if (!intf)
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return 0;
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c = &intf->hw;
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return DPU_REG_READ(c, INTF_LINE_COUNT);
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}
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static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
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unsigned long cap)
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{
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ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine;
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ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch;
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ops->get_status = dpu_hw_intf_get_status;
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ops->enable_timing = dpu_hw_intf_enable_timing_engine;
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ops->get_line_count = dpu_hw_intf_get_line_count;
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}
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static struct dpu_hw_blk_ops dpu_hw_ops;
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struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
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void __iomem *addr,
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struct dpu_mdss_cfg *m)
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{
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struct dpu_hw_intf *c;
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struct dpu_intf_cfg *cfg;
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c = kzalloc(sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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cfg = _intf_offset(idx, m, addr, &c->hw);
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if (IS_ERR_OR_NULL(cfg)) {
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kfree(c);
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pr_err("failed to create dpu_hw_intf %d\n", idx);
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return ERR_PTR(-EINVAL);
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}
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/*
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* Assign ops
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*/
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c->idx = idx;
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c->cap = cfg;
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c->mdss = m;
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_setup_intf_ops(&c->ops, c->cap->features);
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dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops);
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return c;
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}
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void dpu_hw_intf_destroy(struct dpu_hw_intf *intf)
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{
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if (intf)
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dpu_hw_blk_destroy(&intf->base);
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kfree(intf);
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}
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