linux/drivers/clk
James Hogan 778037e1cc clk: clk-divider: fix divisor > 255 bug
Commit 6d9252bd9a (clk: Add support for power of two type dividers)
merged in v3.6 added the _get_val function to convert a divisor value to
a register field value depending on the flags. However it used the type
u8 for the div field, causing divisors larger than 255 to be masked
and the resultant clock rate to be too high.

E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down
to 32.768KHz. The divisor was correctly calculated as 750 (0x2ee). This
was masked to 238 (0xee) resulting in a frequency of 103.26KHz.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: stable@vger.kernel.org
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-08 08:33:12 -08:00
..
keystone
mmp
mvebu
mxs
rockchip
samsung clk: exynos: File scope reg_save array should depend on PM_SLEEP 2013-12-30 18:01:09 +01:00
socfpga
spear
sunxi
tegra
ux500
versatile
x86
zynq
clk-axi-clkgen.c
clk-bcm2835.c
clk-composite.c
clk-devres.c
clk-divider.c clk: clk-divider: fix divisor > 255 bug 2014-01-08 08:33:12 -08:00
clk-efm32gg.c
clk-fixed-factor.c
clk-fixed-rate.c
clk-gate.c clk: wrap I/O access for improved portability 2013-08-27 17:50:38 -07:00
clk-highbank.c
clk-ls1x.c
clk-max77686.c
clk-mux.c
clk-nomadik.c
clk-nspire.c
clk-ppc-corenet.c
clk-prima2.c
clk-s2mps11.c
clk-si5351.c
clk-si5351.h
clk-twl6040.c
clk-u300.c
clk-vt8500.c
clk-wm831x.c
clk-xgene.c
clk.c
clkdev.c
Kconfig
Makefile