Yifan Zha 97a3d6090f drm/amdgpu: Program GC registers through RLCG interface in gfx_v11/gmc_v11 ... [Why] L1 blocks most of GC registers accessing by MMIO. [How] Use RLCG interface to program GC registers under SRIOV VF in full access time. Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-10-18 22:13:24 -04:00
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drm	drm/amdgpu: Program GC registers through RLCG interface in gfx_v11/gmc_v11	2022-10-18 22:13:24 -04:00
host1x
ipu-v3
trace
vga
Makefile