Eugeniy Paltsev 976e78a522 ARC: [plat-axs10x] sdio: Temporary fix of sdio ciu frequency ... DW sdio controller has external ciu clock divider controlled via register in SDIO IP. It divides sdio_ref_clk (which comes from CGU) by 16 for default. So default mmcclk clock (which comes to sdk_in) is 25000000 Hz. So fix wrong current value (50000000 Hz) to actual 25000000 Hz. Note this is a preventive fix, in line with similar change for HSDK where this was actually needed. see: http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002924.html Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2017-10-03 20:36:49 -07:00
..
dts	ARC: [plat-axs10x] sdio: Temporary fix of sdio ciu frequency	2017-10-03 20:36:49 -07:00
.gitignore	ARC: add uImage to .gitignore	2014-03-26 14:31:26 +05:30
Makefile	ARC: [build] Support gz, lzma compressed uImage	2016-10-16 15:49:07 -07:00