linux/drivers/gpu
Jani Nikula 975ee5fca1 drm/i915/dp: cache common rates with sink rates
Now that source rates are static and sink rates are updated whenever
DPCD is updated, we can do and cache the intersection of them whenever
sink rates are updated. This reduces code complexity, as we don't have
to keep calling the functions to intersect. We also get rid of several
common rates arrays on stack.

Limiting the common rates by a max link rate can be done by picking the
first N elements of the cached common rates.

v2: get rid of the local common_rates variable (Manasi)
v3: don't clobber cached eDP rates on short pulse (Ville)

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/e3b287e8cb6559b1f8fd4e80b78a8d22f1802eb7.1491485983.git.jani.nikula@intel.com
2017-04-11 16:54:30 +03:00
..
drm drm/i915/dp: cache common rates with sink rates 2017-04-11 16:54:30 +03:00
host1x gpu: host1x: Set OF node for new host1x devices 2017-01-30 11:47:44 +01:00
ipu-v3 gpu: ipu-v3: only set non-zero AXI ID for IC when PRG is absent 2017-03-16 10:14:49 +01:00
vga Pointer for Markus's image conversion work. 2017-03-14 15:07:33 +01:00
Makefile