forked from Minki/linux
d76271d226
The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort Subsystem. It includes a buffer manager, a video pipeline renderer (blender), an audio mixer and a DisplayPort source controller (transmitter). The DMA engine the provide data to the buffer manager, as well as the DisplayPort PHYs that drive the lanes, are external to the subsystem and interfaced using the DMA engine and PHY APIs respectively. This driver supports the DisplayPort Subsystem and implements - Two planes, for graphics and video - One CRTC that supports alpha blending - One encoder for the DisplayPort transmitter - One connector for an external monitor It currently doesn't support - Color keying - Test pattern generation - Audio - Live input from the Programmable Logic (FPGA) - Output to the Programmable Logic (FPGA) Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 lines
419 B
Plaintext
14 lines
419 B
Plaintext
config DRM_ZYNQMP_DPSUB
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tristate "ZynqMP DisplayPort Controller Driver"
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depends on ARCH_ZYNQMP || COMPILE_TEST
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depends on COMMON_CLK && DRM && OF
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select DMA_ENGINE
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select DRM_GEM_CMA_HELPER
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select DRM_KMS_CMA_HELPER
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select DRM_KMS_HELPER
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select GENERIC_PHY
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help
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This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose
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this option if you have a Xilinx ZynqMP SoC with DisplayPort
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subsystem.
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