efdf72ad5c
The frequency memory bus on Tegra can be adjusted without disabling accesses to memory by updating the memory configuration registers from a per-board table, and then changing the clock frequency. The clock controller and memory controller have an interlock that prevents the new memory registers from taking effect until the clock frequency change. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
71 lines
1.3 KiB
Plaintext
71 lines
1.3 KiB
Plaintext
if ARCH_TEGRA
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comment "NVIDIA Tegra options"
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choice
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prompt "Select Tegra processor family for target system"
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config ARCH_TEGRA_2x_SOC
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bool "Tegra 2 family"
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select CPU_V7
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select ARM_GIC
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select ARCH_REQUIRE_GPIOLIB
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help
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Support for NVIDIA Tegra AP20 and T20 processors, based on the
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ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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endchoice
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config TEGRA_PCI
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bool "PCI Express support"
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select PCI
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comment "Tegra board type"
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config MACH_HARMONY
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bool "Harmony board"
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help
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Support for nVidia Harmony development platform
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config MACH_TRIMSLICE
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bool "TrimSlice board"
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select TEGRA_PCI
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help
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Support for CompuLab TrimSlice platform
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choice
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prompt "Low-level debug console UART"
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default TEGRA_DEBUG_UART_NONE
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config TEGRA_DEBUG_UART_NONE
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bool "None"
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config TEGRA_DEBUG_UARTA
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bool "UART-A"
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config TEGRA_DEBUG_UARTB
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bool "UART-B"
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config TEGRA_DEBUG_UARTC
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bool "UART-C"
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config TEGRA_DEBUG_UARTD
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bool "UART-D"
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config TEGRA_DEBUG_UARTE
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bool "UART-E"
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endchoice
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config TEGRA_SYSTEM_DMA
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bool "Enable system DMA driver for NVIDIA Tegra SoCs"
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default y
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help
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Adds system DMA functionality for NVIDIA Tegra SoCs, used by
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several Tegra device drivers
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endif
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config TEGRA_EMC_SCALING_ENABLE
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bool "Enable scaling the memory frequency"
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