forked from Minki/linux
97347214bc
Introduce reference clock control in MediaTek Chipset in order to disable it if it is not necessary by UFS device to save system power. Currently reference clock can be disabled during system suspend, runtime suspend and clock-gating after link enters hibernate state. Cc: Alim Akhtar <alim.akhtar@samsung.com> Cc: Avri Altman <avri.altman@wdc.com> Cc: Bart Van Assche <bvanassche@acm.org> Cc: Bean Huo <beanhuo@micron.com> Cc: Can Guo <cang@codeaurora.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/1577683950-1702-4-git-send-email-stanley.chu@mediatek.com Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
81 lines
1.7 KiB
C
81 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#ifndef _UFS_MEDIATEK_H
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#define _UFS_MEDIATEK_H
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#include <linux/bitops.h>
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#include <linux/soc/mediatek/mtk_sip_svc.h>
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/*
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* Vendor specific UFSHCI Registers
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*/
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#define REG_UFS_REFCLK_CTRL 0x144
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/*
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* Ref-clk control
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*
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* Values for register REG_UFS_REFCLK_CTRL
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*/
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#define REFCLK_RELEASE 0x0
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#define REFCLK_REQUEST BIT(0)
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#define REFCLK_ACK BIT(1)
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#define REFCLK_REQ_TIMEOUT_MS 3
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/*
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* Vendor specific pre-defined parameters
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*/
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#define UFS_MTK_LIMIT_NUM_LANES_RX 1
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#define UFS_MTK_LIMIT_NUM_LANES_TX 1
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#define UFS_MTK_LIMIT_HSGEAR_RX UFS_HS_G3
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#define UFS_MTK_LIMIT_HSGEAR_TX UFS_HS_G3
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#define UFS_MTK_LIMIT_PWMGEAR_RX UFS_PWM_G4
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#define UFS_MTK_LIMIT_PWMGEAR_TX UFS_PWM_G4
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#define UFS_MTK_LIMIT_RX_PWR_PWM SLOW_MODE
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#define UFS_MTK_LIMIT_TX_PWR_PWM SLOW_MODE
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#define UFS_MTK_LIMIT_RX_PWR_HS FAST_MODE
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#define UFS_MTK_LIMIT_TX_PWR_HS FAST_MODE
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#define UFS_MTK_LIMIT_HS_RATE PA_HS_MODE_B
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#define UFS_MTK_LIMIT_DESIRED_MODE UFS_HS_MODE
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/*
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* Other attributes
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*/
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#define VS_DEBUGCLOCKENABLE 0xD0A1
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#define VS_SAVEPOWERCONTROL 0xD0A6
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#define VS_UNIPROPOWERDOWNCONTROL 0xD0A8
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/*
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* SiP commands
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*/
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#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276)
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#define UFS_MTK_SIP_DEVICE_RESET BIT(1)
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#define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3)
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/*
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* VS_DEBUGCLOCKENABLE
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*/
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enum {
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TX_SYMBOL_CLK_REQ_FORCE = 5,
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};
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/*
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* VS_SAVEPOWERCONTROL
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*/
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enum {
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RX_SYMBOL_CLK_GATE_EN = 0,
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SYS_CLK_GATE_EN = 2,
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TX_CLK_GATE_EN = 3,
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};
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struct ufs_mtk_host {
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struct ufs_hba *hba;
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struct phy *mphy;
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bool ref_clk_enabled;
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};
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#endif /* !_UFS_MEDIATEK_H */
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