forked from Minki/linux
96a2b40c7b
While the two bits for link, duplex or RGMII delays are used the same
way on chips supporting the said feature, the two bits for speed have
different meaning for most of the chips out there.
Speed value is stored in bits 1:0, 0x3 means unforce (normal detection).
Some chips reuse values for alternative speeds when bit 12 is set.
Newer chips with speed > 1Gbps reuse value 0x3 thus need a new bit 13.
Here are the values to write in register 0x1 to (un)force speed:
| Speed | 88E6065 | 88E6185 | 88E6352 | 88E6390 | 88E6390X |
| ------- | ------- | ------- | ------- | ------- | -------- |
| 10 | 0x0000 | 0x0000 | 0x0000 | 0x2000 | 0x2000 |
| 100 | 0x0001 | 0x0001 | 0x0001 | 0x2001 | 0x2001 |
| 200 | 0x0002 | NA | 0x1001 | 0x3001 | 0x3001 |
| 1000 | NA | 0x0002 | 0x0002 | 0x2002 | 0x2002 |
| 2500 | NA | NA | NA | 0x3003 | 0x3003 |
| 10000 | NA | NA | NA | NA | 0x2003 |
| unforce | 0x0003 | 0x0003 | 0x0003 | 0x0000 | 0x0000 |
This patch implements a generic mv88e6xxx_port_set_speed() function used
by chip-specific wrappers to filter supported ports and speeds.
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
53 lines
2.0 KiB
C
53 lines
2.0 KiB
C
/*
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* Marvell 88E6xxx Switch Port Registers support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _MV88E6XXX_PORT_H
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#define _MV88E6XXX_PORT_H
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#include "mv88e6xxx.h"
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int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
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u16 *val);
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int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
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u16 val);
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int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
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phy_interface_t mode);
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int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
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phy_interface_t mode);
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int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);
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int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup);
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int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
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int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
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int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
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int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
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int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
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int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
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int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);
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int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid);
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int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);
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int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid);
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int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);
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int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
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u16 mode);
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#endif /* _MV88E6XXX_PORT_H */
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