071e5aceeb
- Reset controllers: Adding support for Microchip Sparx5 Switch. - Memory controllers: ARM Primecell PL35x SMC memory controller driver cleanups and improvements. - i.MX SoC drivers: Power domain support for i.MX8MM and i.MX8MN. - Rockchip: RK3568 power domains support + DT binding updates, cleanups. - Qualcomm SoC drivers: Amend socinfo with more SoC/PMIC details, including support for MSM8226, MDM9607, SM6125 and SC8180X. - ARM FFA driver: "Firmware Framework for ARMv8-A", defining management interfaces and communication (including bus model) between partitions both in Normal and Secure Worlds. - Tegra Memory controller changes, including major rework to deal with identity mappings at boot and integration with ARM SMMU pieces. -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAmDokgYPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx3looP/20uQAjRadPJFdV/B2mpZYqXMI4dIN9g7KJ1 6uEoaGurzYWQQreDXswQ5vFUcQfIudEJ9Im9IF+9BUsFQ2uvPTJ4I+HDN++WH70B cIsmwwBr7Q4JUVP+O7T2WGtBY69jvHTpJrCCVtyHtwEyL4a1uyfelsAJXbxqaqis w1lmXNkkSqx5c67H3maNNDRnbutyLL2gO0TYdiBapOcc5V03OYKNnMbDqRTddqyt 4UH4eYkFkNai8UJ476BXHU9ldlWzEkRBib/OKwF9k3oPj9W3kdQ/vd2IKK5a1fTX jIbOPSRRC8K/9Bxn1KEtdoU0Yy+rlm3xd7DtQl5RyGTD+tHVq3dN55WjoXBY83Yh r37y7uII9i09tPg5+APSX/jgodsIt4c46dKwvYuWXvB7ziomfsKxQiRanApJG6UX qS5NCUrlfYWlL302JOTvEtDBePXXiXQ065GuRjM948WMnVzXwEKwYUakGhvXQWMS jXCcOGW7GhnbY3+Ipn9chyhydHpKSxIb8oBk4cMRJU9jlN2GmjHgW8RMvT2WM6VF 1F8acyMvf6en5tV6f23cjbW+iIMTS5egKNfqi8tdjGVxbowypyJYzjYOhaqk6veJ jHOmpglTXas0QD3ZRU7vGVlrvHqik8XyRsq3N9CQjVenRCbsQLKZRi1gTbIuspcR rejqH3Fs =kPg8 -----END PGP SIGNATURE----- Merge tag 'arm-drivers-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM driver updates from Olof Johansson: - Reset controllers: Adding support for Microchip Sparx5 Switch. - Memory controllers: ARM Primecell PL35x SMC memory controller driver cleanups and improvements. - i.MX SoC drivers: Power domain support for i.MX8MM and i.MX8MN. - Rockchip: RK3568 power domains support + DT binding updates, cleanups. - Qualcomm SoC drivers: Amend socinfo with more SoC/PMIC details, including support for MSM8226, MDM9607, SM6125 and SC8180X. - ARM FFA driver: "Firmware Framework for ARMv8-A", defining management interfaces and communication (including bus model) between partitions both in Normal and Secure Worlds. - Tegra Memory controller changes, including major rework to deal with identity mappings at boot and integration with ARM SMMU pieces. * tag 'arm-drivers-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (120 commits) firmware: turris-mox-rwtm: add marvell,armada-3700-rwtm-firmware compatible string firmware: turris-mox-rwtm: show message about HWRNG registration firmware: turris-mox-rwtm: fail probing when firmware does not support hwrng firmware: turris-mox-rwtm: report failures better firmware: turris-mox-rwtm: fix reply status decoding function soc: imx: gpcv2: add support for i.MX8MN power domains dt-bindings: add defines for i.MX8MN power domains firmware: tegra: bpmp: Fix Tegra234-only builds iommu/arm-smmu: Use Tegra implementation on Tegra186 iommu/arm-smmu: tegra: Implement SID override programming iommu/arm-smmu: tegra: Detect number of instances at runtime dt-bindings: arm-smmu: Add Tegra186 compatible string firmware: qcom_scm: Add MDM9607 compatible soc: qcom: rpmpd: Add MDM9607 RPM Power Domains soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's dt-bindings: soc: rockchip: drop unnecessary #phy-cells from grf.yaml memory: emif: remove unused frequency and voltage notifiers memory: fsl_ifc: fix leak of private memory on probe failure memory: fsl_ifc: fix leak of IO mapping on probe failure ...
126 lines
3.3 KiB
YAML
126 lines
3.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/fsl,imx-gpcv2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX General Power Controller v2
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maintainers:
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- Andrey Smirnov <andrew.smirnov@gmail.com>
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description: |
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The i.MX7S/D General Power Control (GPC) block contains Power Gating
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Control (PGC) for various power domains.
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Power domains contained within GPC node are generic power domain
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providers, documented in
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Documentation/devicetree/bindings/power/power-domain.yaml, which are
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described as subnodes of the power gating controller 'pgc' node.
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IP cores belonging to a power domain should contain a 'power-domains'
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property that is a phandle for PGC node representing the domain.
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properties:
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compatible:
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enum:
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- fsl,imx7d-gpc
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- fsl,imx8mn-gpc
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- fsl,imx8mq-gpc
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- fsl,imx8mm-gpc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 3
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pgc:
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type: object
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description: list of power domains provided by this controller.
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patternProperties:
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"power-domain@[0-9]$":
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type: object
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properties:
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'#power-domain-cells':
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const: 0
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reg:
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description: |
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Power domain index. Valid values are defined in
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include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
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include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
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include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc
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maxItems: 1
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clocks:
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description: |
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A number of phandles to clocks that need to be enabled during domain
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power-up sequencing to ensure reset propagation into devices located
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inside this power domain.
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minItems: 1
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maxItems: 5
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power-supply: true
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resets:
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description: |
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A number of phandles to resets that need to be asserted during
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power-up sequencing of the domain. The resets belong to devices
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located inside the power domain, which need to be held in reset
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across the power-up sequence. So no means to specify what each
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reset is in a generic power-domain binding.
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minItems: 1
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maxItems: 4
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required:
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- '#power-domain-cells'
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- reg
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required:
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- compatible
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- reg
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- interrupts
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- pgc
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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gpc@303a0000 {
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compatible = "fsl,imx7d-gpc";
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reg = <0x303a0000 0x1000>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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pgc {
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#address-cells = <1>;
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#size-cells = <0>;
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pgc_mipi_phy: power-domain@0 {
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#power-domain-cells = <0>;
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reg = <0>;
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power-supply = <®_1p0d>;
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};
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pgc_pcie_phy: power-domain@1 {
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#power-domain-cells = <0>;
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reg = <1>;
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power-supply = <®_1p0d>;
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};
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pgc_hsic_phy: power-domain@2 {
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#power-domain-cells = <0>;
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reg = <2>;
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power-supply = <®_1p2>;
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};
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};
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};
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