forked from Minki/linux
94bf91baf3
Sync DMA descriptor before hitting the TX mailbox for weak memory model CPUs. There has been discussions several years ago about this. Some believe that writel() should guarantee ordering. Others want explicit barriers if necessary. Today writel() does not have the ordering guarantee and many other drivers use explicit barriers. Signed-off-by: Vlad Zolotarov <vlad@scalemp.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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.. | ||
bnx2x | ||
b44.c | ||
b44.h | ||
bcm63xx_enet.c | ||
bcm63xx_enet.h | ||
bnx2_fw.h | ||
bnx2.c | ||
bnx2.h | ||
cnic_defs.h | ||
cnic_if.h | ||
cnic.c | ||
cnic.h | ||
Kconfig | ||
Makefile | ||
sb1250-mac.c | ||
tg3.c | ||
tg3.h |