forked from Minki/linux
ac5f0f3f86
Armada 3700 SoC comprise a single XOR engine compliant with the ones used in older Marvell SoC's like Armada XP or 38x. The only thing that needs modification is the Mbus configuration, which has to be done on two levels: global and in device. The first one is inherited from the bootloader. The latter can be opened in a default way, leaving arbitration to the bus controller. Hence filled mbus_dram_target_info structure is not needed. Patch "dmaengine: mv_xor: optimize performance by using a subset of the XOR channels" introduced limitation for using XOR engines and channels vs number of available CPU's. Those constraints do not however fit Armada 3700 architecture with two possible CPU's and single, dual-channel engine. Hence in this commit an adjustment for setting maximum available channels is added. This patch enables XOR access to DRAM by opening default window to 4GB space with specific attribute. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
42 lines
1.2 KiB
Plaintext
42 lines
1.2 KiB
Plaintext
* Marvell XOR engines
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Required properties:
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- compatible: Should be one of the following:
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- "marvell,orion-xor"
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- "marvell,armada-380-xor"
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- "marvell,armada-3700-xor".
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- reg: Should contain registers location and length (two sets)
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the first set is the low registers, the second set the high
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registers for the XOR engine.
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- clocks: pointer to the reference clock
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The DT node must also contains sub-nodes for each XOR channel that the
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XOR engine has. Those sub-nodes have the following required
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properties:
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- interrupts: interrupt of the XOR channel
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The sub-nodes used to contain one or several of the following
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properties, but they are now deprecated:
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- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
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- dmacap,memset to indicate that the XOR channel is capable of memset operations
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- dmacap,xor to indicate that the XOR channel is capable of xor operations
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- dmacap,interrupt to indicate that the XOR channel is capable of
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generating interrupts
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Example:
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xor@d0060900 {
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compatible = "marvell,orion-xor";
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reg = <0xd0060900 0x100
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0xd0060b00 0x100>;
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clocks = <&coreclk 0>;
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status = "okay";
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xor00 {
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interrupts = <51>;
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};
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xor01 {
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interrupts = <52>;
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};
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};
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