937d3f58ca
When the CPU enters a low power mode, the TRFCR_EL1 contents could be reset. Thus we need to save/restore the TRFCR_EL1 along with the ETM4x registers to allow the tracing. The TRFCR related helpers are in a new header file, as we need to use them for TRBE in the later patches. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210914102641.1852544-2-suzuki.poulose@arm.com [Fixed cosmetic details] Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
25 lines
443 B
C
25 lines
443 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Arm v8 Self-Hosted trace support.
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*
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* Copyright (C) 2021 ARM Ltd.
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*/
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#ifndef __CORESIGHT_SELF_HOSTED_TRACE_H
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#define __CORESIGHT_SELF_HOSTED_TRACE_H
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#include <asm/sysreg.h>
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static inline u64 read_trfcr(void)
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{
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return read_sysreg_s(SYS_TRFCR_EL1);
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}
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static inline void write_trfcr(u64 val)
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{
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write_sysreg_s(val, SYS_TRFCR_EL1);
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isb();
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}
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#endif /* __CORESIGHT_SELF_HOSTED_TRACE_H */
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