forked from Minki/linux
6a077e4ab9
Not saving PAR is an unfortunate oversight. If the guest performs
an AT* operation and gets scheduled out before reading the result
of the translation from PAR, it could become corrupted by another
guest or the host.
Saving this register is made slightly more complicated as KVM also
uses it on the permission fault handling path, leading to an ugly
"stash and restore" sequence. Fortunately, this is already a slow
path so we don't really care. Also, Linux doesn't do any AT*
operation, so Linux guests are not impacted by this bug.
[ Slightly tweaked to use an even register as first operand to ldrd
and strd operations in interrupts_head.S - Christoffer ]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
84 lines
3.1 KiB
C
84 lines
3.1 KiB
C
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __ARM_KVM_ASM_H__
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#define __ARM_KVM_ASM_H__
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/* 0 is reserved as an invalid value. */
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#define c0_MPIDR 1 /* MultiProcessor ID Register */
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#define c0_CSSELR 2 /* Cache Size Selection Register */
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#define c1_SCTLR 3 /* System Control Register */
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#define c1_ACTLR 4 /* Auxilliary Control Register */
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#define c1_CPACR 5 /* Coprocessor Access Control */
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#define c2_TTBR0 6 /* Translation Table Base Register 0 */
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#define c2_TTBR0_high 7 /* TTBR0 top 32 bits */
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#define c2_TTBR1 8 /* Translation Table Base Register 1 */
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#define c2_TTBR1_high 9 /* TTBR1 top 32 bits */
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#define c2_TTBCR 10 /* Translation Table Base Control R. */
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#define c3_DACR 11 /* Domain Access Control Register */
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#define c5_DFSR 12 /* Data Fault Status Register */
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#define c5_IFSR 13 /* Instruction Fault Status Register */
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#define c5_ADFSR 14 /* Auxilary Data Fault Status R */
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#define c5_AIFSR 15 /* Auxilary Instrunction Fault Status R */
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#define c6_DFAR 16 /* Data Fault Address Register */
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#define c6_IFAR 17 /* Instruction Fault Address Register */
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#define c7_PAR 18 /* Physical Address Register */
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#define c7_PAR_high 19 /* PAR top 32 bits */
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#define c9_L2CTLR 20 /* Cortex A15 L2 Control Register */
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#define c10_PRRR 21 /* Primary Region Remap Register */
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#define c10_NMRR 22 /* Normal Memory Remap Register */
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#define c12_VBAR 23 /* Vector Base Address Register */
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#define c13_CID 24 /* Context ID Register */
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#define c13_TID_URW 25 /* Thread ID, User R/W */
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#define c13_TID_URO 26 /* Thread ID, User R/O */
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#define c13_TID_PRIV 27 /* Thread ID, Privileged */
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#define c14_CNTKCTL 28 /* Timer Control Register (PL1) */
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#define NR_CP15_REGS 29 /* Number of regs (incl. invalid) */
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#define ARM_EXCEPTION_RESET 0
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#define ARM_EXCEPTION_UNDEFINED 1
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#define ARM_EXCEPTION_SOFTWARE 2
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#define ARM_EXCEPTION_PREF_ABORT 3
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#define ARM_EXCEPTION_DATA_ABORT 4
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#define ARM_EXCEPTION_IRQ 5
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#define ARM_EXCEPTION_FIQ 6
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#define ARM_EXCEPTION_HVC 7
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#ifndef __ASSEMBLY__
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struct kvm;
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struct kvm_vcpu;
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extern char __kvm_hyp_init[];
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extern char __kvm_hyp_init_end[];
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extern char __kvm_hyp_exit[];
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extern char __kvm_hyp_exit_end[];
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extern char __kvm_hyp_vector[];
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extern char __kvm_hyp_code_start[];
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extern char __kvm_hyp_code_end[];
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extern void __kvm_flush_vm_context(void);
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extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
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extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
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#endif
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#endif /* __ARM_KVM_ASM_H__ */
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