forked from Minki/linux
79d57bf6fa
Interrupt commands causes the CP to trigger an interrupt as the command is processed, regardless of the GPU being done processing previous commands. This is seen by the interrupt being delivered before the fence is written on 8974 and is likely the cause of the additional CP_WAIT_FOR_IDLE workaround found for a306, which would cause the CP to wait for the GPU to go idle before triggering the interrupt. Instead we can set the (undocumented) BIT(31) of the CACHE_FLUSH_TS which will cause a special CACHE_FLUSH_TS interrupt to be triggered from the GPU as the write event is processed. Add CACHE_FLUSH_TS to the IRQ masks of A3xx and A4xx and remove the workaround for A306. Suggested-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
585 lines
15 KiB
C
585 lines
15 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/pm_opp.h>
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#include "adreno_gpu.h"
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#include "msm_gem.h"
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#include "msm_mmu.h"
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int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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switch (param) {
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case MSM_PARAM_GPU_ID:
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*value = adreno_gpu->info->revn;
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return 0;
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case MSM_PARAM_GMEM_SIZE:
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*value = adreno_gpu->gmem;
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return 0;
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case MSM_PARAM_GMEM_BASE:
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*value = 0x100000;
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return 0;
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case MSM_PARAM_CHIP_ID:
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*value = adreno_gpu->rev.patchid |
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(adreno_gpu->rev.minor << 8) |
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(adreno_gpu->rev.major << 16) |
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(adreno_gpu->rev.core << 24);
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return 0;
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case MSM_PARAM_MAX_FREQ:
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*value = adreno_gpu->base.fast_rate;
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return 0;
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case MSM_PARAM_TIMESTAMP:
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if (adreno_gpu->funcs->get_timestamp) {
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int ret;
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pm_runtime_get_sync(&gpu->pdev->dev);
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ret = adreno_gpu->funcs->get_timestamp(gpu, value);
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pm_runtime_put_autosuspend(&gpu->pdev->dev);
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return ret;
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}
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return -EINVAL;
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case MSM_PARAM_NR_RINGS:
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*value = gpu->nr_rings;
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return 0;
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default:
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DBG("%s: invalid param: %u", gpu->name, param);
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return -EINVAL;
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}
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}
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const struct firmware *
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adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
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{
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struct drm_device *drm = adreno_gpu->base.dev;
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const struct firmware *fw = NULL;
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char newname[strlen("qcom/") + strlen(fwname) + 1];
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int ret;
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sprintf(newname, "qcom/%s", fwname);
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/*
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* Try first to load from qcom/$fwfile using a direct load (to avoid
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* a potential timeout waiting for usermode helper)
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*/
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if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
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(adreno_gpu->fwloc == FW_LOCATION_NEW)) {
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ret = request_firmware_direct(&fw, newname, drm->dev);
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if (!ret) {
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dev_info(drm->dev, "loaded %s from new location\n",
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newname);
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adreno_gpu->fwloc = FW_LOCATION_NEW;
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return fw;
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} else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
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dev_err(drm->dev, "failed to load %s: %d\n",
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newname, ret);
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return ERR_PTR(ret);
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}
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}
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/*
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* Then try the legacy location without qcom/ prefix
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*/
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if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
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(adreno_gpu->fwloc == FW_LOCATION_LEGACY)) {
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ret = request_firmware_direct(&fw, fwname, drm->dev);
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if (!ret) {
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dev_info(drm->dev, "loaded %s from legacy location\n",
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newname);
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adreno_gpu->fwloc = FW_LOCATION_LEGACY;
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return fw;
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} else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
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dev_err(drm->dev, "failed to load %s: %d\n",
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fwname, ret);
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return ERR_PTR(ret);
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}
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}
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/*
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* Finally fall back to request_firmware() for cases where the
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* usermode helper is needed (I think mainly android)
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*/
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if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
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(adreno_gpu->fwloc == FW_LOCATION_HELPER)) {
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ret = request_firmware(&fw, newname, drm->dev);
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if (!ret) {
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dev_info(drm->dev, "loaded %s with helper\n",
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newname);
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adreno_gpu->fwloc = FW_LOCATION_HELPER;
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return fw;
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} else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
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dev_err(drm->dev, "failed to load %s: %d\n",
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newname, ret);
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return ERR_PTR(ret);
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}
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}
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dev_err(drm->dev, "failed to load %s\n", fwname);
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return ERR_PTR(-ENOENT);
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}
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static int adreno_load_fw(struct adreno_gpu *adreno_gpu)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) {
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const struct firmware *fw;
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if (!adreno_gpu->info->fw[i])
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continue;
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/* Skip if the firmware has already been loaded */
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if (adreno_gpu->fw[i])
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continue;
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fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]);
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if (IS_ERR(fw))
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return PTR_ERR(fw);
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adreno_gpu->fw[i] = fw;
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}
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return 0;
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}
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struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
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const struct firmware *fw, u64 *iova)
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{
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struct drm_gem_object *bo;
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void *ptr;
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ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4,
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MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
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if (IS_ERR(ptr))
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return ERR_CAST(ptr);
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memcpy(ptr, &fw->data[4], fw->size - 4);
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msm_gem_put_vaddr(bo);
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return bo;
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}
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int adreno_hw_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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int ret, i;
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DBG("%s", gpu->name);
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ret = adreno_load_fw(adreno_gpu);
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if (ret)
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return ret;
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for (i = 0; i < gpu->nr_rings; i++) {
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struct msm_ringbuffer *ring = gpu->rb[i];
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if (!ring)
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continue;
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ret = msm_gem_get_iova(ring->bo, gpu->aspace, &ring->iova);
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if (ret) {
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ring->iova = 0;
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dev_err(gpu->dev->dev,
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"could not map ringbuffer %d: %d\n", i, ret);
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return ret;
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}
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ring->cur = ring->start;
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ring->next = ring->start;
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/* reset completed fence seqno: */
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ring->memptrs->fence = ring->seqno;
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ring->memptrs->rptr = 0;
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}
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/*
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* Setup REG_CP_RB_CNTL. The same value is used across targets (with
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* the excpetion of A430 that disables the RPTR shadow) - the cacluation
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* for the ringbuffer size and block size is moved to msm_gpu.h for the
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* pre-processor to deal with and the A430 variant is ORed in here
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*/
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adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
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MSM_GPU_RB_CNTL_DEFAULT |
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(adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
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/* Setup ringbuffer address - use ringbuffer[0] for GPU init */
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adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE,
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REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova);
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if (!adreno_is_a430(adreno_gpu)) {
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adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
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REG_ADRENO_CP_RB_RPTR_ADDR_HI,
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rbmemptr(gpu->rb[0], rptr));
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}
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return 0;
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}
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/* Use this helper to read rptr, since a430 doesn't update rptr in memory */
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static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
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struct msm_ringbuffer *ring)
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{
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if (adreno_is_a430(adreno_gpu))
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return ring->memptrs->rptr = adreno_gpu_read(
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adreno_gpu, REG_ADRENO_CP_RB_RPTR);
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else
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return ring->memptrs->rptr;
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}
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struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
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{
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return gpu->rb[0];
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}
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void adreno_recover(struct msm_gpu *gpu)
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{
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struct drm_device *dev = gpu->dev;
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int ret;
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// XXX pm-runtime?? we *need* the device to be off after this
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// so maybe continuing to call ->pm_suspend/resume() is better?
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gpu->funcs->pm_suspend(gpu);
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gpu->funcs->pm_resume(gpu);
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ret = msm_gpu_hw_init(gpu);
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if (ret) {
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dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
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/* hmm, oh well? */
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}
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}
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void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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struct msm_file_private *ctx)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct msm_drm_private *priv = gpu->dev->dev_private;
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struct msm_ringbuffer *ring = submit->ring;
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unsigned i;
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for (i = 0; i < submit->nr_cmds; i++) {
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switch (submit->cmd[i].type) {
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case MSM_SUBMIT_CMD_IB_TARGET_BUF:
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/* ignore IB-targets */
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break;
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case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
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/* ignore if there has not been a ctx switch: */
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if (priv->lastctx == ctx)
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break;
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case MSM_SUBMIT_CMD_BUF:
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OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
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CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
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OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
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OUT_RING(ring, submit->cmd[i].size);
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OUT_PKT2(ring);
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break;
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}
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}
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OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
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OUT_RING(ring, submit->seqno);
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if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
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/* Flush HLSQ lazy updates to make sure there is nothing
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* pending for indirect loads after the timestamp has
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* passed:
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*/
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OUT_PKT3(ring, CP_EVENT_WRITE, 1);
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OUT_RING(ring, HLSQ_FLUSH);
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OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
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OUT_RING(ring, 0x00000000);
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}
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/* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
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OUT_PKT3(ring, CP_EVENT_WRITE, 3);
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OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));
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OUT_RING(ring, rbmemptr(ring, fence));
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OUT_RING(ring, submit->seqno);
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#if 0
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if (adreno_is_a3xx(adreno_gpu)) {
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/* Dummy set-constant to trigger context rollover */
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
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OUT_RING(ring, 0x00000000);
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}
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#endif
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gpu->funcs->flush(gpu, ring);
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}
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void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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uint32_t wptr;
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/* Copy the shadow to the actual register */
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ring->cur = ring->next;
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/*
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* Mask wptr value that we calculate to fit in the HW range. This is
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* to account for the possibility that the last command fit exactly into
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* the ringbuffer and rb->next hasn't wrapped to zero yet
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*/
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wptr = get_wptr(ring);
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/* ensure writes to ringbuffer have hit system memory: */
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mb();
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adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
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}
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bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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uint32_t wptr = get_wptr(ring);
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/* wait for CP to drain ringbuffer: */
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if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
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return true;
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/* TODO maybe we need to reset GPU here to recover from hang? */
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DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
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gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
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return false;
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}
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#ifdef CONFIG_DEBUG_FS
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void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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int i;
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seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
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adreno_gpu->info->revn, adreno_gpu->rev.core,
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adreno_gpu->rev.major, adreno_gpu->rev.minor,
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adreno_gpu->rev.patchid);
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for (i = 0; i < gpu->nr_rings; i++) {
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struct msm_ringbuffer *ring = gpu->rb[i];
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seq_printf(m, "rb %d: fence: %d/%d\n", i,
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ring->memptrs->fence, ring->seqno);
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seq_printf(m, " rptr: %d\n",
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get_rptr(adreno_gpu, ring));
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seq_printf(m, "rb wptr: %d\n", get_wptr(ring));
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}
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/* dump these out in a form that can be parsed by demsm: */
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seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
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for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
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uint32_t start = adreno_gpu->registers[i];
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uint32_t end = adreno_gpu->registers[i+1];
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uint32_t addr;
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for (addr = start; addr <= end; addr++) {
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uint32_t val = gpu_read(gpu, addr);
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seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
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}
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}
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}
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#endif
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/* Dump common gpu status and scratch registers on any hang, to make
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* the hangcheck logs more useful. The scratch registers seem always
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* safe to read when GPU has hung (unlike some other regs, depending
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* on how the GPU hung), and they are useful to match up to cmdstream
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* dumps when debugging hangs:
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*/
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void adreno_dump_info(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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int i;
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printk("revision: %d (%d.%d.%d.%d)\n",
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adreno_gpu->info->revn, adreno_gpu->rev.core,
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adreno_gpu->rev.major, adreno_gpu->rev.minor,
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adreno_gpu->rev.patchid);
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for (i = 0; i < gpu->nr_rings; i++) {
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struct msm_ringbuffer *ring = gpu->rb[i];
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printk("rb %d: fence: %d/%d\n", i,
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ring->memptrs->fence,
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ring->seqno);
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printk("rptr: %d\n", get_rptr(adreno_gpu, ring));
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printk("rb wptr: %d\n", get_wptr(ring));
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}
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}
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/* would be nice to not have to duplicate the _show() stuff with printk(): */
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void adreno_dump(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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int i;
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/* dump these out in a form that can be parsed by demsm: */
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printk("IO:region %s 00000000 00020000\n", gpu->name);
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for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
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uint32_t start = adreno_gpu->registers[i];
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uint32_t end = adreno_gpu->registers[i+1];
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uint32_t addr;
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for (addr = start; addr <= end; addr++) {
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uint32_t val = gpu_read(gpu, addr);
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printk("IO:R %08x %08x\n", addr<<2, val);
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}
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}
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}
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static uint32_t ring_freewords(struct msm_ringbuffer *ring)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
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uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
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/* Use ring->next to calculate free size */
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uint32_t wptr = ring->next - ring->start;
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uint32_t rptr = get_rptr(adreno_gpu, ring);
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return (rptr + (size - 1) - wptr) % size;
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}
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void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
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{
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|
if (spin_until(ring_freewords(ring) >= ndwords))
|
|
DRM_DEV_ERROR(ring->gpu->dev->dev,
|
|
"timeout waiting for space in ringbuffer %d\n",
|
|
ring->id);
|
|
}
|
|
|
|
/* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
|
|
static int adreno_get_legacy_pwrlevels(struct device *dev)
|
|
{
|
|
struct device_node *child, *node;
|
|
int ret;
|
|
|
|
node = of_find_compatible_node(dev->of_node, NULL,
|
|
"qcom,gpu-pwrlevels");
|
|
if (!node) {
|
|
dev_err(dev, "Could not find the GPU powerlevels\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
for_each_child_of_node(node, child) {
|
|
unsigned int val;
|
|
|
|
ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
|
|
if (ret)
|
|
continue;
|
|
|
|
/*
|
|
* Skip the intentionally bogus clock value found at the bottom
|
|
* of most legacy frequency tables
|
|
*/
|
|
if (val != 27000000)
|
|
dev_pm_opp_add(dev, val, 0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int adreno_get_pwrlevels(struct device *dev,
|
|
struct msm_gpu *gpu)
|
|
{
|
|
unsigned long freq = ULONG_MAX;
|
|
struct dev_pm_opp *opp;
|
|
int ret;
|
|
|
|
gpu->fast_rate = 0;
|
|
|
|
/* You down with OPP? */
|
|
if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
|
|
ret = adreno_get_legacy_pwrlevels(dev);
|
|
else {
|
|
ret = dev_pm_opp_of_add_table(dev);
|
|
if (ret)
|
|
dev_err(dev, "Unable to set the OPP table\n");
|
|
}
|
|
|
|
if (!ret) {
|
|
/* Find the fastest defined rate */
|
|
opp = dev_pm_opp_find_freq_floor(dev, &freq);
|
|
if (!IS_ERR(opp)) {
|
|
gpu->fast_rate = freq;
|
|
dev_pm_opp_put(opp);
|
|
}
|
|
}
|
|
|
|
if (!gpu->fast_rate) {
|
|
dev_warn(dev,
|
|
"Could not find a clock rate. Using a reasonable default\n");
|
|
/* Pick a suitably safe clock speed for any target */
|
|
gpu->fast_rate = 200000000;
|
|
}
|
|
|
|
DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|
struct adreno_gpu *adreno_gpu,
|
|
const struct adreno_gpu_funcs *funcs, int nr_rings)
|
|
{
|
|
struct adreno_platform_config *config = pdev->dev.platform_data;
|
|
struct msm_gpu_config adreno_gpu_config = { 0 };
|
|
struct msm_gpu *gpu = &adreno_gpu->base;
|
|
|
|
adreno_gpu->funcs = funcs;
|
|
adreno_gpu->info = adreno_info(config->rev);
|
|
adreno_gpu->gmem = adreno_gpu->info->gmem;
|
|
adreno_gpu->revn = adreno_gpu->info->revn;
|
|
adreno_gpu->rev = config->rev;
|
|
|
|
adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
|
|
adreno_gpu_config.irqname = "kgsl_3d0_irq";
|
|
|
|
adreno_gpu_config.va_start = SZ_16M;
|
|
adreno_gpu_config.va_end = 0xffffffff;
|
|
|
|
adreno_gpu_config.nr_rings = nr_rings;
|
|
|
|
adreno_get_pwrlevels(&pdev->dev, gpu);
|
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, DRM_MSM_INACTIVE_PERIOD);
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
|
|
adreno_gpu->info->name, &adreno_gpu_config);
|
|
}
|
|
|
|
void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
|
|
release_firmware(adreno_gpu->fw[i]);
|
|
|
|
msm_gpu_cleanup(&adreno_gpu->base);
|
|
}
|