forked from Minki/linux
bd0b9ac405
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
358 lines
8.7 KiB
C
358 lines
8.7 KiB
C
/*
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* ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
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*
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* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <linux/spinlock.h>
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#include <asm/mcip.h>
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static char smp_cpuinfo_buf[128];
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static int idu_detected;
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static DEFINE_RAW_SPINLOCK(mcip_lock);
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/*
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* Any SMP specific init any CPU does when it comes up.
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* Here we setup the CPU to enable Inter-Processor-Interrupts
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* Called for each CPU
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* -Master : init_IRQ()
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* -Other(s) : start_kernel_secondary()
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*/
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void mcip_init_smp(unsigned int cpu)
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{
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smp_ipi_irq_setup(cpu, IPI_IRQ);
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}
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static void mcip_ipi_send(int cpu)
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{
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unsigned long flags;
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int ipi_was_pending;
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/*
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* NOTE: We must spin here if the other cpu hasn't yet
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* serviced a previous message. This can burn lots
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* of time, but we MUST follows this protocol or
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* ipi messages can be lost!!!
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* Also, we must release the lock in this loop because
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* the other side may get to this same loop and not
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* be able to ack -- thus causing deadlock.
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*/
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do {
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);
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ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
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if (ipi_was_pending == 0)
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break; /* break out but keep lock */
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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} while (1);
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__mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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#ifdef CONFIG_ARC_IPI_DBG
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if (ipi_was_pending)
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pr_info("IPI ACK delayed from cpu %d\n", cpu);
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#endif
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}
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static void mcip_ipi_clear(int irq)
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{
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unsigned int cpu, c;
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unsigned long flags;
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unsigned int __maybe_unused copy;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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/* Who sent the IPI */
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__mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0);
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copy = cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */
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/*
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* In rare case, multiple concurrent IPIs sent to same target can
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* possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be
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* "vectored" (multiple bits sets) as opposed to typical single bit
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*/
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do {
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c = __ffs(cpu); /* 0,1,2,3 */
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__mcip_cmd(CMD_INTRPT_GENERATE_ACK, c);
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cpu &= ~(1U << c);
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} while (cpu);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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#ifdef CONFIG_ARC_IPI_DBG
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if (c != __ffs(copy))
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pr_info("IPIs from %x coalesced to %x\n",
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copy, raw_smp_processor_id());
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#endif
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}
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volatile int wake_flag;
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static void mcip_wakeup_cpu(int cpu, unsigned long pc)
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{
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BUG_ON(cpu == 0);
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wake_flag = cpu;
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}
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void arc_platform_smp_wait_to_boot(int cpu)
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{
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while (wake_flag != cpu)
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;
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wake_flag = 0;
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__asm__ __volatile__("j @first_lines_of_secondary \n");
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}
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struct plat_smp_ops plat_smp_ops = {
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.info = smp_cpuinfo_buf,
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.cpu_kick = mcip_wakeup_cpu,
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.ipi_send = mcip_ipi_send,
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.ipi_clear = mcip_ipi_clear,
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};
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void mcip_init_early_smp(void)
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{
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#define IS_AVAIL1(var, str) ((var) ? str : "")
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struct mcip_bcr {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad3:8,
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idu:1, llm:1, num_cores:6,
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iocoh:1, grtc:1, dbg:1, pad2:1,
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msg:1, sem:1, ipi:1, pad:1,
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ver:8;
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#else
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unsigned int ver:8,
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pad:1, ipi:1, sem:1, msg:1,
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pad2:1, dbg:1, grtc:1, iocoh:1,
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num_cores:6, llm:1, idu:1,
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pad3:8;
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#endif
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} mp;
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READ_BCR(ARC_REG_MCIP_BCR, mp);
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sprintf(smp_cpuinfo_buf,
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"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
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mp.ver, mp.num_cores,
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IS_AVAIL1(mp.ipi, "IPI "),
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IS_AVAIL1(mp.idu, "IDU "),
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IS_AVAIL1(mp.dbg, "DEBUG "),
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IS_AVAIL1(mp.grtc, "GRTC"));
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idu_detected = mp.idu;
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if (mp.dbg) {
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__mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
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__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
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}
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if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc)
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panic("kernel trying to use non-existent GRTC\n");
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}
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/***************************************************************************
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* ARCv2 Interrupt Distribution Unit (IDU)
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*
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* Connects external "COMMON" IRQs to core intc, providing:
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* -dynamic routing (IRQ affinity)
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* -load balancing (Round Robin interrupt distribution)
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* -1:N distribution
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*
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* It physically resides in the MCIP hw block
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*/
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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/*
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* Set the DEST for @cmn_irq to @cpu_mask (1 bit per core)
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*/
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static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
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{
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__mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
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}
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static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
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unsigned int distr)
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{
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union {
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unsigned int word;
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struct {
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unsigned int distr:2, pad:2, lvl:1, pad2:27;
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};
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} data;
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data.distr = distr;
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data.lvl = lvl;
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__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
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}
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static void idu_irq_mask(struct irq_data *data)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static void idu_irq_unmask(struct irq_data *data)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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#ifdef CONFIG_SMP
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static int
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idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
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bool force)
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{
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unsigned long flags;
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cpumask_t online;
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/* errout if no online cpu per @cpumask */
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if (!cpumask_and(&online, cpumask, cpu_online_mask))
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return -EINVAL;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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idu_set_dest(data->hwirq, cpumask_bits(&online)[0]);
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idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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return IRQ_SET_MASK_OK;
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}
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#endif
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static struct irq_chip idu_irq_chip = {
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.name = "MCIP IDU Intc",
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.irq_mask = idu_irq_mask,
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.irq_unmask = idu_irq_unmask,
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#ifdef CONFIG_SMP
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.irq_set_affinity = idu_irq_set_affinity,
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#endif
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};
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static int idu_first_irq;
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static void idu_cascade_isr(struct irq_desc *desc)
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{
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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unsigned int core_irq = irq_desc_get_irq(desc);
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unsigned int idu_irq;
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idu_irq = core_irq - idu_first_irq;
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generic_handle_irq(irq_find_mapping(domain, idu_irq));
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}
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static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq);
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irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
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return 0;
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}
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static int idu_irq_xlate(struct irq_domain *d, struct device_node *n,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_type)
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{
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irq_hw_number_t hwirq = *out_hwirq = intspec[0];
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int distri = intspec[1];
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unsigned long flags;
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*out_type = IRQ_TYPE_NONE;
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/* XXX: validate distribution scheme again online cpu mask */
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if (distri == 0) {
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/* 0 - Round Robin to all cpus, otherwise 1 bit per core */
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raw_spin_lock_irqsave(&mcip_lock, flags);
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idu_set_dest(hwirq, BIT(num_online_cpus()) - 1);
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idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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} else {
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/*
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* DEST based distribution for Level Triggered intr can only
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* have 1 CPU, so generalize it to always contain 1 cpu
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*/
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int cpu = ffs(distri);
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if (cpu != fls(distri))
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pr_warn("IDU irq %lx distri mode set to cpu %x\n",
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hwirq, cpu);
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raw_spin_lock_irqsave(&mcip_lock, flags);
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idu_set_dest(hwirq, cpu);
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idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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return 0;
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}
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static const struct irq_domain_ops idu_irq_ops = {
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.xlate = idu_irq_xlate,
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.map = idu_irq_map,
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};
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/*
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* [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI)
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* [24, 23+C]: If C > 0 then "C" common IRQs
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* [24+C, N]: Not statically assigned, private-per-core
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*/
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static int __init
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idu_of_init(struct device_node *intc, struct device_node *parent)
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{
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struct irq_domain *domain;
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/* Read IDU BCR to confirm nr_irqs */
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int nr_irqs = of_irq_count(intc);
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int i, irq;
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if (!idu_detected)
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panic("IDU not detected, but DeviceTree using it");
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pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
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domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
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/* Parent interrupts (core-intc) are already mapped */
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for (i = 0; i < nr_irqs; i++) {
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/*
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* Return parent uplink IRQs (towards core intc) 24,25,.....
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* this step has been done before already
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* however we need it to get the parent virq and set IDU handler
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* as first level isr
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*/
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irq = irq_of_parse_and_map(intc, i);
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if (!i)
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idu_first_irq = irq;
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irq_set_chained_handler_and_data(irq, idu_cascade_isr, domain);
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}
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__mcip_cmd(CMD_IDU_ENABLE, 0);
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return 0;
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}
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IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init);
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