forked from Minki/linux
925bb17b72
This patch converts the remaining sh7722 clocks to use clkdev for lookup. The now unused name and id from struct clk are also removed. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
289 lines
7.9 KiB
C
289 lines
7.9 KiB
C
/*
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* arch/sh/kernel/cpu/sh4a/clock-sh7722.c
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*
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* SH7722 clock framework support
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*
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* Copyright (C) 2009 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <asm/clkdev.h>
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#include <asm/clock.h>
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#include <asm/hwblk.h>
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#include <cpu/sh7722.h>
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/* SH7722 registers */
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#define FRQCR 0xa4150000
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#define VCLKCR 0xa4150004
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#define SCLKACR 0xa4150008
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#define SCLKBCR 0xa415000c
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#define IRDACLKCR 0xa4150018
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#define PLLCR 0xa4150024
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#define DLLFRQ 0xa4150050
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/* Fixed 32 KHz root clock for RTC and Power Management purposes */
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static struct clk r_clk = {
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.rate = 32768,
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};
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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struct clk extal_clk = {
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.rate = 33333333,
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};
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/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
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static unsigned long dll_recalc(struct clk *clk)
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{
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unsigned long mult;
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if (__raw_readl(PLLCR) & 0x1000)
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mult = __raw_readl(DLLFRQ);
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else
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mult = 0;
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return clk->parent->rate * mult;
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}
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static struct clk_ops dll_clk_ops = {
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.recalc = dll_recalc,
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};
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static struct clk dll_clk = {
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.ops = &dll_clk_ops,
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.parent = &r_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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unsigned long div = 1;
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if (__raw_readl(PLLCR) & 0x4000)
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mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
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else
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div = 2;
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return (clk->parent->rate * mult) / div;
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}
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static struct clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll_clk = {
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.ops = &pll_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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};
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struct clk *main_clks[] = {
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&r_clk,
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&extal_clk,
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&dll_clk,
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&pll_clk,
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};
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static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
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static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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.multipliers = multipliers,
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.nr_multipliers = ARRAY_SIZE(multipliers),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
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};
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enum { DIV4_IRDA, DIV4_ENABLE_NR };
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struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
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[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
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};
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enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
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struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
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[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
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[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
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};
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enum { DIV6_V, DIV6_NR };
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struct clk div6_clks[DIV6_NR] = {
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[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
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};
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static struct clk mstp_clks[HWBLK_NR] = {
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SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
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SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
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SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
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SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
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SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
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};
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#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("rclk", &r_clk),
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("dll_clk", &dll_clk),
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CLKDEV_CON_ID("pll_clk", &pll_clk),
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/* DIV4 clocks */
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
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CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
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CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
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CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
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CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
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CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
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CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
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/* DIV6 clocks */
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CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
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/* MSTP clocks */
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CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
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CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
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{
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/* TMU0 */
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.dev_id = "sh_tmu.0",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[HWBLK_TMU],
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}, {
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/* TMU1 */
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.dev_id = "sh_tmu.1",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[HWBLK_TMU],
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}, {
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/* TMU2 */
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.dev_id = "sh_tmu.2",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[HWBLK_TMU],
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},
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CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
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CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
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CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
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{
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/* SCIF0 */
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.dev_id = "sh-sci.0",
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.con_id = "sci_fck",
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.clk = &mstp_clks[HWBLK_SCIF0],
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}, {
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/* SCIF1 */
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.dev_id = "sh-sci.1",
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.con_id = "sci_fck",
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.clk = &mstp_clks[HWBLK_SCIF1],
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}, {
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/* SCIF2 */
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.dev_id = "sh-sci.2",
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.con_id = "sci_fck",
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.clk = &mstp_clks[HWBLK_SCIF2],
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},
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CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
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CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
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CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
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CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
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CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
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CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
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CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
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CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
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CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
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CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
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CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
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CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
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CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
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CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
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};
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int __init arch_clk_init(void)
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{
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int k, ret = 0;
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/* autodetect extal or dll configuration */
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if (__raw_readl(PLLCR) & 0x1000)
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pll_clk.parent = &dll_clk;
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else
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pll_clk.parent = &extal_clk;
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div4_enable_register(div4_enable_clks,
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DIV4_ENABLE_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div4_reparent_register(div4_reparent_clks,
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DIV4_REPARENT_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div6_register(div6_clks, DIV6_NR);
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if (!ret)
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ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
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return ret;
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}
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