According to the Schematic, the hardware of ci20 leads to uart3, but not to uart2. Uart2 is miswritten in the original code. Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips <linux-mips@vger.kernel.org> Cc: linux-kernel <linux-kernel@vger.kernel.org> Cc: devicetree@vger.kernel.org Cc: robh+dt@kernel.org Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: mark.rutland@arm.com Cc: malat@debian.org Cc: ezequiel@collabora.co.uk Cc: ulf.hansson@linaro.org Cc: syq <syq@debian.org> Cc: jiaxun.yang <jiaxun.yang@flygoat.com>
		
			
				
	
	
		
			241 lines
		
	
	
		
			3.9 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			241 lines
		
	
	
		
			3.9 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0
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| /dts-v1/;
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| 
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| #include "jz4780.dtsi"
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| #include <dt-bindings/gpio/gpio.h>
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| 
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| / {
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| 	compatible = "img,ci20", "ingenic,jz4780";
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| 
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| 	aliases {
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| 		serial0 = &uart0;
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| 		serial1 = &uart1;
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| 		serial3 = &uart3;
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| 		serial4 = &uart4;
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| 	};
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| 
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| 	chosen {
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| 		stdout-path = &uart4;
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| 	};
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| 
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| 	memory {
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| 		device_type = "memory";
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| 		reg = <0x0 0x10000000
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| 		       0x30000000 0x30000000>;
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| 	};
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| 
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| 	eth0_power: fixedregulator@0 {
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| 		compatible = "regulator-fixed";
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| 		regulator-name = "eth0_power";
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| 		gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
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| 		enable-active-high;
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| 	};
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| };
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| 
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| &ext {
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| 	clock-frequency = <48000000>;
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| };
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| 
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| &mmc0 {
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| 	status = "okay";
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| 
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| 	bus-width = <4>;
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| 	max-frequency = <50000000>;
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| 
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&pins_mmc0>;
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| 
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| 	cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>;
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| };
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| 
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| &mmc1 {
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| 	status = "okay";
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| 
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| 	bus-width = <4>;
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| 	max-frequency = <50000000>;
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| 
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&pins_mmc1>;
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| };
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| 
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| &uart0 {
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| 	status = "okay";
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| 
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&pins_uart0>;
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| };
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| 
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| &uart1 {
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| 	status = "okay";
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| 
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&pins_uart1>;
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| };
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| 
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| &uart3 {
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| 	status = "okay";
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| 
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&pins_uart3>;
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| };
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| 
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| &uart4 {
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| 	status = "okay";
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| 
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&pins_uart4>;
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| };
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| 
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| &nemc {
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| 	status = "okay";
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| 
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| 	nandc: nand-controller@1 {
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| 		compatible = "ingenic,jz4780-nand";
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| 		reg = <1 0 0x1000000>;
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| 
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| 		#address-cells = <1>;
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| 		#size-cells = <0>;
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| 
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| 		ingenic,bch-controller = <&bch>;
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| 
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| 		ingenic,nemc-tAS = <10>;
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| 		ingenic,nemc-tAH = <5>;
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| 		ingenic,nemc-tBP = <10>;
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| 		ingenic,nemc-tAW = <15>;
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| 		ingenic,nemc-tSTRV = <100>;
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| 
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| 		/*
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| 		 * Only CLE/ALE are needed for the devices that are connected, rather
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| 		 * than the full address line set.
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| 		 */
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| 		pinctrl-names = "default";
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| 		pinctrl-0 = <&pins_nemc>;
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| 
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| 		nand@1 {
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| 			reg = <1>;
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| 
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| 			nand-ecc-step-size = <1024>;
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| 			nand-ecc-strength = <24>;
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| 			nand-ecc-mode = "hw";
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| 			nand-on-flash-bbt;
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| 
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| 			pinctrl-names = "default";
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| 			pinctrl-0 = <&pins_nemc_cs1>;
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| 
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| 			partitions {
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| 				compatible = "fixed-partitions";
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| 				#address-cells = <2>;
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| 				#size-cells = <2>;
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| 
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| 				partition@0 {
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| 					label = "u-boot-spl";
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| 					reg = <0x0 0x0 0x0 0x800000>;
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| 				};
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| 
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| 				partition@800000 {
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| 					label = "u-boot";
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| 					reg = <0x0 0x800000 0x0 0x200000>;
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| 				};
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| 
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| 				partition@a00000 {
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| 					label = "u-boot-env";
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| 					reg = <0x0 0xa00000 0x0 0x200000>;
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| 				};
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| 
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| 				partition@c00000 {
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| 					label = "boot";
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| 					reg = <0x0 0xc00000 0x0 0x4000000>;
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| 				};
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| 
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| 				partition@4c00000 {
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| 					label = "system";
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| 					reg = <0x0 0x4c00000 0x1 0xfb400000>;
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| 				};
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| 			};
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| 		};
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| 	};
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| 
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| 	dm9000@6 {
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| 		compatible = "davicom,dm9000";
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| 		davicom,no-eeprom;
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| 
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| 		pinctrl-names = "default";
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| 		pinctrl-0 = <&pins_nemc_cs6>;
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| 
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| 		reg = <6 0 1   /* addr */
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| 		       6 2 1>; /* data */
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| 
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| 		ingenic,nemc-tAS = <15>;
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| 		ingenic,nemc-tAH = <10>;
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| 		ingenic,nemc-tBP = <20>;
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| 		ingenic,nemc-tAW = <50>;
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| 		ingenic,nemc-tSTRV = <100>;
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| 
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| 		reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
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| 		vcc-supply = <ð0_power>;
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| 
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| 		interrupt-parent = <&gpe>;
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| 		interrupts = <19 4>;
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| 	};
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| };
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| 
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| &bch {
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| 	status = "okay";
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| };
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| 
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| &pinctrl {
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| 	pins_uart0: uart0 {
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| 		function = "uart0";
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| 		groups = "uart0-data";
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| 		bias-disable;
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| 	};
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| 
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| 	pins_uart1: uart1 {
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| 		function = "uart1";
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| 		groups = "uart1-data";
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| 		bias-disable;
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| 	};
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| 
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| 	pins_uart3: uart3 {
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| 		function = "uart3";
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| 		groups = "uart3-data", "uart3-hwflow";
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| 		bias-disable;
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| 	};
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| 
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| 	pins_uart4: uart4 {
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| 		function = "uart4";
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| 		groups = "uart4-data";
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| 		bias-disable;
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| 	};
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| 
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| 	pins_nemc: nemc {
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| 		function = "nemc";
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| 		groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe";
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| 		bias-disable;
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| 	};
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| 
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| 	pins_nemc_cs1: nemc-cs1 {
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| 		function = "nemc-cs1";
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| 		groups = "nemc-cs1";
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| 		bias-disable;
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| 	};
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| 
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| 	pins_nemc_cs6: nemc-cs6 {
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| 		function = "nemc-cs6";
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| 		groups = "nemc-cs6";
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| 		bias-disable;
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| 	};
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| 
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| 	pins_mmc0: mmc0 {
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| 		function = "mmc0";
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| 		groups = "mmc0-1bit-e", "mmc0-4bit-e";
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| 		bias-disable;
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| 	};
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| 
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| 	pins_mmc1: mmc1 {
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| 		function = "mmc1";
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| 		groups = "mmc1-1bit-d", "mmc1-4bit-d";
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| 		bias-disable;
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| 	};
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| };
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