b9683c21f6
It was duplicated across multiple generations. Reviewed-by: Alex Xie <AlexBin.Xie@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
94 lines
3.1 KiB
C
94 lines
3.1 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_GFX_H__
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#define __AMDGPU_GFX_H__
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int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
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void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
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void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
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unsigned max_sh);
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void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
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int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
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struct amdgpu_ring *ring,
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struct amdgpu_irq_src *irq);
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void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
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struct amdgpu_irq_src *irq);
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void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
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int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
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unsigned hpd_size);
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int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
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unsigned mqd_size);
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void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev);
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/**
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* amdgpu_gfx_create_bitmask - create a bitmask
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*
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* @bit_width: length of the mask
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*
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* create a variable length bit mask.
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* Returns the bitmask.
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*/
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static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
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{
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return (u32)((1ULL << bit_width) - 1);
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}
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static inline int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev,
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int mec, int pipe, int queue)
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{
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int bit = 0;
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bit += mec * adev->gfx.mec.num_pipe_per_mec
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* adev->gfx.mec.num_queue_per_pipe;
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bit += pipe * adev->gfx.mec.num_queue_per_pipe;
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bit += queue;
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return bit;
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}
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static inline void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
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int *mec, int *pipe, int *queue)
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{
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*queue = bit % adev->gfx.mec.num_queue_per_pipe;
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*pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
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% adev->gfx.mec.num_pipe_per_mec;
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*mec = (bit / adev->gfx.mec.num_queue_per_pipe)
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/ adev->gfx.mec.num_pipe_per_mec;
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}
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static inline bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
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int mec, int pipe, int queue)
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{
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return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue),
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adev->gfx.mec.queue_bitmap);
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}
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#endif
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