4d34686eb6
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
109 lines
3.0 KiB
C
109 lines
3.0 KiB
C
/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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static void
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pwr_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
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struct nvkm_perfctr *ctr)
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{
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u32 mask = 0x00000000;
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u32 ctrl = 0x00000001;
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int i;
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for (i = 0; i < ARRAY_SIZE(ctr->signal) && ctr->signal[i]; i++)
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mask |= 1 << (ctr->signal[i] - dom->signal);
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nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask);
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nv_wr32(ppm, 0x10a50c + (ctr->slot * 0x10), ctrl);
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nv_wr32(ppm, 0x10a50c + (ppm->last * 0x10), 0x00000003);
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}
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static void
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pwr_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
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struct nvkm_perfctr *ctr)
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{
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ctr->ctr = ppm->pwr[ctr->slot];
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ctr->clk = ppm->pwr[ppm->last];
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}
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static void
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pwr_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom)
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{
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int i;
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for (i = 0; i <= ppm->last; i++) {
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ppm->pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10));
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nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x80000000);
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}
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}
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static const struct nvkm_funcdom
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pwr_perfctr_func = {
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.init = pwr_perfctr_init,
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.read = pwr_perfctr_read,
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.next = pwr_perfctr_next,
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};
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const struct nvkm_specdom
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gt215_pm_pwr[] = {
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{ 0x20, (const struct nvkm_specsig[]) {
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{ 0x00, "pwr_gr_idle" },
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{ 0x04, "pwr_bsp_idle" },
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{ 0x05, "pwr_vp_idle" },
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{ 0x06, "pwr_ppp_idle" },
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{ 0x13, "pwr_ce0_idle" },
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{}
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}, &pwr_perfctr_func },
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{}
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};
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const struct nvkm_specdom
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gf100_pm_pwr[] = {
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{ 0x20, (const struct nvkm_specsig[]) {
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{ 0x00, "pwr_gr_idle" },
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{ 0x04, "pwr_bsp_idle" },
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{ 0x05, "pwr_vp_idle" },
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{ 0x06, "pwr_ppp_idle" },
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{ 0x13, "pwr_ce0_idle" },
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{ 0x14, "pwr_ce1_idle" },
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{}
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}, &pwr_perfctr_func },
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{}
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};
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const struct nvkm_specdom
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gk104_pm_pwr[] = {
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{ 0x20, (const struct nvkm_specsig[]) {
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{ 0x00, "pwr_gr_idle" },
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{ 0x04, "pwr_bsp_idle" },
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{ 0x05, "pwr_vp_idle" },
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{ 0x06, "pwr_ppp_idle" },
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{ 0x13, "pwr_ce0_idle" },
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{ 0x14, "pwr_ce1_idle" },
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{ 0x15, "pwr_ce2_idle" },
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{}
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}, &pwr_perfctr_func },
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{}
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};
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