c4e8428673
The number of AE2FUNC_MAP registers is different in every QAT device (c62x, c3xxx and dh895xcc) although the logic and the register offsets are the same across devices. This patch separates the logic that configures the iov threads in a common function that takes as input the number of AE2FUNC_MAP registers supported by a device. The function is then added to the adf_hw_device_data structure of each device, and called with the appropriate parameters. The configure iov thread logic is added to a new file, adf_gen2_hw_data.c, that is going to contain code that is shared across QAT GEN2 devices. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
51 lines
2.0 KiB
C
51 lines
2.0 KiB
C
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2014 - 2020 Intel Corporation */
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#ifndef ADF_DH895x_HW_DATA_H_
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#define ADF_DH895x_HW_DATA_H_
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/* PCIe configuration space */
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#define ADF_DH895XCC_SRAM_BAR 0
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#define ADF_DH895XCC_PMISC_BAR 1
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#define ADF_DH895XCC_ETR_BAR 2
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#define ADF_DH895XCC_RX_RINGS_OFFSET 8
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#define ADF_DH895XCC_TX_RINGS_MASK 0xFF
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#define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000
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#define ADF_DH895XCC_FUSECTL_SKU_SHIFT 20
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#define ADF_DH895XCC_FUSECTL_SKU_1 0x0
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#define ADF_DH895XCC_FUSECTL_SKU_2 0x1
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#define ADF_DH895XCC_FUSECTL_SKU_3 0x2
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#define ADF_DH895XCC_FUSECTL_SKU_4 0x3
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#define ADF_DH895XCC_MAX_ACCELERATORS 6
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#define ADF_DH895XCC_MAX_ACCELENGINES 12
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#define ADF_DH895XCC_ACCELERATORS_REG_OFFSET 13
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#define ADF_DH895XCC_ACCELERATORS_MASK 0x3F
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#define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF
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#define ADF_DH895XCC_ETR_MAX_BANKS 32
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#define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
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#define ADF_DH895XCC_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
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#define ADF_DH895XCC_SMIA0_MASK 0xFFFFFFFF
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#define ADF_DH895XCC_SMIA1_MASK 0x1
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/* Error detection and correction */
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#define ADF_DH895XCC_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
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#define ADF_DH895XCC_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960)
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#define ADF_DH895XCC_ENABLE_AE_ECC_ERR BIT(28)
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#define ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
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#define ADF_DH895XCC_UERRSSMSH(i) (i * 0x4000 + 0x18)
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#define ADF_DH895XCC_CERRSSMSH(i) (i * 0x4000 + 0x10)
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#define ADF_DH895XCC_ERRSSMSH_EN BIT(3)
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#define ADF_DH895XCC_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04))
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#define ADF_DH895XCC_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i) * 0x04))
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/* AE to function mapping */
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#define ADF_DH895XCC_AE2FUNC_MAP_GRP_A_NUM_REGS 96
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#define ADF_DH895XCC_AE2FUNC_MAP_GRP_B_NUM_REGS 12
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/* FW names */
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#define ADF_DH895XCC_FW "qat_895xcc.bin"
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#define ADF_DH895XCC_MMP "qat_895xcc_mmp.bin"
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void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data);
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void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data);
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#endif
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