forked from Minki/linux
243abbf2a6
This patch cleans up the documentation of the device-tree binding for the Flexcan devices on Freescale's PowerPC and ARM cores. Extra properties are not used by the driver so we are removing them. Signed-off-by: Robin Holt <holt@sgi.com> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>, Acked-by: Wolfgang Grandegger <wg@grandegger.com>, Cc: U Bhaskar-B22300 <B22300@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: socketcan-core@lists.berlios.de, Cc: netdev@vger.kernel.org, Cc: PPC list <linuxppc-dev@lists.ozlabs.org> Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: David S. Miller <davem@davemloft.net>
275 lines
5.9 KiB
Plaintext
275 lines
5.9 KiB
Plaintext
/*
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* P1010 RDB Device Tree Source
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "p1010si.dtsi"
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/ {
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model = "fsl,P1010RDB";
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compatible = "fsl,P1010RDB";
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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pci0 = &pci0;
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pci1 = &pci1;
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can0 = &can0;
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can1 = &can1;
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};
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memory {
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device_type = "memory";
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};
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ifc@ffe1e000 {
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/* NOR, NAND Flashes and CPLD on board */
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ranges = <0x0 0x0 0x0 0xee000000 0x02000000
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0x1 0x0 0x0 0xff800000 0x00010000
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0x3 0x0 0x0 0xffb00000 0x00000020>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x2000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@40000 {
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/* 256KB for DTB Image */
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reg = <0x00040000 0x00040000>;
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label = "NOR DTB Image";
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};
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partition@80000 {
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/* 7 MB for Linux Kernel Image */
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reg = <0x00080000 0x00700000>;
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label = "NOR Linux Kernel Image";
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};
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partition@800000 {
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/* 20MB for JFFS2 based Root file System */
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reg = <0x00800000 0x01400000>;
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label = "NOR JFFS2 Root File System";
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};
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partition@1f00000 {
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/* This location must not be altered */
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/* 512KB for u-boot Bootloader Image */
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/* 512KB for u-boot Environment Variables */
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reg = <0x01f00000 0x00100000>;
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label = "NOR U-Boot Image";
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read-only;
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};
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};
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nand@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,ifc-nand";
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reg = <0x1 0x0 0x10000>;
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partition@0 {
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/* This location must not be altered */
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/* 1MB for u-boot Bootloader Image */
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reg = <0x0 0x00100000>;
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label = "NAND U-Boot Image";
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read-only;
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};
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partition@100000 {
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/* 1MB for DTB Image */
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reg = <0x00100000 0x00100000>;
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label = "NAND DTB Image";
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};
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partition@200000 {
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/* 4MB for Linux Kernel Image */
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reg = <0x00200000 0x00400000>;
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label = "NAND Linux Kernel Image";
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};
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partition@600000 {
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/* 4MB for Compressed Root file System Image */
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reg = <0x00600000 0x00400000>;
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label = "NAND Compressed RFS Image";
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};
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partition@a00000 {
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/* 15MB for JFFS2 based Root file System */
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reg = <0x00a00000 0x00f00000>;
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label = "NAND JFFS2 Root File System";
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};
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partition@1900000 {
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/* 7MB for User Area */
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reg = <0x01900000 0x00700000>;
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label = "NAND User area";
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};
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};
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cpld@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p1010rdb-cpld";
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reg = <0x3 0x0 0x0000020>;
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bank-width = <1>;
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device-width = <1>;
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};
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};
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soc@ffe00000 {
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spi@7000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25sl12801";
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reg = <0>;
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spi-max-frequency = <50000000>;
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partition@0 {
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/* 1MB for u-boot Bootloader Image */
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/* 1MB for Environment */
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reg = <0x0 0x00100000>;
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label = "SPI Flash U-Boot Image";
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read-only;
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};
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partition@100000 {
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/* 512KB for DTB Image */
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reg = <0x00100000 0x00080000>;
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label = "SPI Flash DTB Image";
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};
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partition@180000 {
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/* 4MB for Linux Kernel Image */
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reg = <0x00180000 0x00400000>;
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label = "SPI Flash Linux Kernel Image";
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};
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partition@580000 {
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/* 4MB for Compressed RFS Image */
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reg = <0x00580000 0x00400000>;
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label = "SPI Flash Compressed RFSImage";
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};
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partition@980000 {
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/* 6.5MB for JFFS2 based RFS */
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reg = <0x00980000 0x00680000>;
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label = "SPI Flash JFFS2 RFS";
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};
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};
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};
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usb@22000 {
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phy_type = "utmi";
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};
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mdio@24000 {
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <3 1>;
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reg = <0x1>;
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1>;
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reg = <0x0>;
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1>;
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reg = <0x2>;
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};
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};
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enet0: ethernet@b0000 {
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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enet1: ethernet@b1000 {
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phy-handle = <&phy1>;
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tbi-handle = <&tbi0>;
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phy-connection-type = "sgmii";
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};
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enet2: ethernet@b2000 {
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phy-handle = <&phy2>;
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tbi-handle = <&tbi1>;
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phy-connection-type = "sgmii";
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};
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};
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pci0: pcie@ffe09000 {
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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pcie@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0x0 0x0 0x1 &mpic 0x4 0x1
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0000 0x0 0x0 0x2 &mpic 0x5 0x1
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0000 0x0 0x0 0x3 &mpic 0x6 0x1
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0000 0x0 0x0 0x4 &mpic 0x7 0x1
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>;
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@ffe0a000 {
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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pcie@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0x0 0x0 0x1 &mpic 0x4 0x1
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0000 0x0 0x0 0x2 &mpic 0x5 0x1
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0000 0x0 0x0 0x3 &mpic 0x6 0x1
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0000 0x0 0x0 0x4 &mpic 0x7 0x1
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>;
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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};
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