Ville Syrjälä 901c2daf05 drm/i915: Put back lane_count into intel_dp and add link_rate too ... With MST there won't be a crtc assigned to the main link encoder, so trying to dig up the pipe_config from there is a recipe for an oops. Instead store the parameters (lane_count and link_rate) in the encoder, and use those values during link training etc. Since those parameters are now assigned only when the link is actually enabled, .compute_config() won't clobber them as it did before. Hardware state readout is still bonkers though as we don't transfer the link parameters from pipe_config intel_dp. We should do that during encoder sanitation. But since we don't even do a proper job of reading out the main link encoder state for MST there's littel point in worrying about this now. Fixes a regression with MST caused by: commit 90a6b7b052 Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Mon Jul 6 16:39:15 2015 +0300 drm/i915: Move intel_dp->lane_count into pipe_config v2: Different apporoach that should keep intel_dp_check_mst_status() somewhat less oopsy Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reported-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2015-08-26 09:58:19 +02:00
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drm	drm/i915: Put back lane_count into intel_dp and add link_rate too	2015-08-26 09:58:19 +02:00
host1x	gpu: host1x: Export host1x_syncpt_read()	2015-04-02 18:46:20 +02:00
ipu-v3	GPU: ipu: fix lockup caused by pending chained interrupts	2015-07-10 11:02:46 +02:00
vga
Makefile	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00