5545b6d1ba
Add device tree bindings for SiFive FU540 L2 cache controller driver Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
52 lines
1.6 KiB
Plaintext
52 lines
1.6 KiB
Plaintext
SiFive L2 Cache Controller
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--------------------------
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The SiFive Level 2 Cache Controller is used to provide access to fast copies
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of memory for masters in a Core Complex. The Level 2 Cache Controller also
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acts as directory-based coherency manager.
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All the properties in ePAPR/DeviceTree specification applies for this platform
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Required Properties:
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--------------------
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- compatible: Should be "sifive,fu540-c000-ccache" and "cache"
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- cache-block-size: Specifies the block size in bytes of the cache.
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Should be 64
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- cache-level: Should be set to 2 for a level 2 cache
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- cache-sets: Specifies the number of associativity sets of the cache.
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Should be 1024
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- cache-size: Specifies the size in bytes of the cache. Should be 2097152
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- cache-unified: Specifies the cache is a unified cache
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- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals)
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- reg: Physical base address and size of L2 cache controller registers map
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Optional Properties:
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--------------------
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- next-level-cache: phandle to the next level cache if present.
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- memory-region: reference to the reserved-memory for the L2 Loosely Integrated
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Memory region. The reserved memory node should be defined as per the bindings
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in reserved-memory.txt
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Example:
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cache-controller@2010000 {
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compatible = "sifive,fu540-c000-ccache", "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <1024>;
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cache-size = <2097152>;
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cache-unified;
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interrupt-parent = <&plic0>;
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interrupts = <1 2 3>;
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reg = <0x0 0x2010000 0x0 0x1000>;
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next-level-cache = <&L25 &L40 &L36>;
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memory-region = <&l2_lim>;
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};
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