f6a8eaca0e
For mdp5, the irqs of hdmi/eDP/dsi0/dsi1 blocks get routed through the
mdp block. In order to decouple hdmi/eDP/etc, register an irq domain
in mdp5. When hdmi/dsi/etc are used with mdp4, they can directly setup
their irqs in their DT nodes as normal. When used with mdp5, instead
set the mdp device as the interrupt-parent, as in:
mdp: qcom,mdss_mdp@fd900000 {
compatible = "qcom,mdss_mdp";
interrupt-controller;
#interrupt-cells = <1>;
...
};
hdmi: qcom,hdmi_tx@fd922100 {
compatible = "qcom,hdmi-tx-8074";
interrupt-parent = <&mdp>;
interrupts = <8 0>; /* MDP5_HW_INTR_STATUS.INTR_HDMI */
...
};
There is a slight awkwardness, in that we cannot disable child irqs
at the mdp level, they can only be cleared in the child block. So
you must not use threaded irq handlers in the child. I'm not sure
if there is a better way to deal with that.
Signed-off-by: Rob Clark <robdclark@gmail.com>
199 lines
5.0 KiB
C
199 lines
5.0 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include "msm_drv.h"
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#include "mdp5_kms.h"
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void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask)
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{
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mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask);
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}
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static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
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{
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DRM_ERROR("errors: %08x\n", irqstatus);
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}
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void mdp5_irq_preinstall(struct msm_kms *kms)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
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mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff);
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}
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int mdp5_irq_postinstall(struct msm_kms *kms)
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{
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struct mdp_kms *mdp_kms = to_mdp_kms(kms);
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
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struct mdp_irq *error_handler = &mdp5_kms->error_handler;
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error_handler->irq = mdp5_irq_error_handler;
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error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN |
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MDP5_IRQ_INTF1_UNDER_RUN |
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MDP5_IRQ_INTF2_UNDER_RUN |
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MDP5_IRQ_INTF3_UNDER_RUN;
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mdp_irq_register(mdp_kms, error_handler);
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return 0;
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}
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void mdp5_irq_uninstall(struct msm_kms *kms)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
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mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
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}
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static void mdp5_irq_mdp(struct mdp_kms *mdp_kms)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
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struct drm_device *dev = mdp5_kms->dev;
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struct msm_drm_private *priv = dev->dev_private;
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unsigned int id;
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uint32_t status;
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status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS);
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mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status);
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VERB("status=%08x", status);
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mdp_dispatch_irqs(mdp_kms, status);
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for (id = 0; id < priv->num_crtcs; id++)
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if (status & mdp5_crtc_vblank(priv->crtcs[id]))
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drm_handle_vblank(dev, id);
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}
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irqreturn_t mdp5_irq(struct msm_kms *kms)
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{
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struct mdp_kms *mdp_kms = to_mdp_kms(kms);
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
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uint32_t intr;
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intr = mdp5_read(mdp5_kms, REG_MDP5_HW_INTR_STATUS);
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VERB("intr=%08x", intr);
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if (intr & MDP5_HW_INTR_STATUS_INTR_MDP) {
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mdp5_irq_mdp(mdp_kms);
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intr &= ~MDP5_HW_INTR_STATUS_INTR_MDP;
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}
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while (intr) {
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irq_hw_number_t hwirq = fls(intr) - 1;
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generic_handle_irq(irq_find_mapping(
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mdp5_kms->irqcontroller.domain, hwirq));
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intr &= ~(1 << hwirq);
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}
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return IRQ_HANDLED;
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}
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int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
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{
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mdp_update_vblank_mask(to_mdp_kms(kms),
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mdp5_crtc_vblank(crtc), true);
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return 0;
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}
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void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
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{
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mdp_update_vblank_mask(to_mdp_kms(kms),
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mdp5_crtc_vblank(crtc), false);
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}
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/*
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* interrupt-controller implementation, so sub-blocks (hdmi/eDP/dsi/etc)
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* can register to get their irq's delivered
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*/
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#define VALID_IRQS (MDP5_HW_INTR_STATUS_INTR_DSI0 | \
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MDP5_HW_INTR_STATUS_INTR_DSI1 | \
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MDP5_HW_INTR_STATUS_INTR_HDMI | \
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MDP5_HW_INTR_STATUS_INTR_EDP)
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static void mdp5_hw_mask_irq(struct irq_data *irqd)
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{
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struct mdp5_kms *mdp5_kms = irq_data_get_irq_chip_data(irqd);
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smp_mb__before_atomic();
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clear_bit(irqd->hwirq, &mdp5_kms->irqcontroller.enabled_mask);
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smp_mb__after_atomic();
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}
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static void mdp5_hw_unmask_irq(struct irq_data *irqd)
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{
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struct mdp5_kms *mdp5_kms = irq_data_get_irq_chip_data(irqd);
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smp_mb__before_atomic();
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set_bit(irqd->hwirq, &mdp5_kms->irqcontroller.enabled_mask);
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smp_mb__after_atomic();
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}
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static struct irq_chip mdp5_hw_irq_chip = {
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.name = "mdp5",
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.irq_mask = mdp5_hw_mask_irq,
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.irq_unmask = mdp5_hw_unmask_irq,
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};
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static int mdp5_hw_irqdomain_map(struct irq_domain *d,
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unsigned int irq, irq_hw_number_t hwirq)
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{
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struct mdp5_kms *mdp5_kms = d->host_data;
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if (!(VALID_IRQS & (1 << hwirq)))
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return -EPERM;
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irq_set_chip_and_handler(irq, &mdp5_hw_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, mdp5_kms);
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set_irq_flags(irq, IRQF_VALID);
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return 0;
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}
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static struct irq_domain_ops mdp5_hw_irqdomain_ops = {
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.map = mdp5_hw_irqdomain_map,
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.xlate = irq_domain_xlate_onecell,
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};
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int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms)
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{
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struct device *dev = mdp5_kms->dev->dev;
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struct irq_domain *d;
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d = irq_domain_add_linear(dev->of_node, 32,
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&mdp5_hw_irqdomain_ops, mdp5_kms);
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if (!d) {
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dev_err(dev, "mdp5 irq domain add failed\n");
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return -ENXIO;
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}
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mdp5_kms->irqcontroller.enabled_mask = 0;
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mdp5_kms->irqcontroller.domain = d;
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return 0;
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}
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void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms)
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{
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if (mdp5_kms->irqcontroller.domain) {
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irq_domain_remove(mdp5_kms->irqcontroller.domain);
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mdp5_kms->irqcontroller.domain = NULL;
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}
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}
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