forked from Minki/linux
8ff1d5718e
Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
780 lines
26 KiB
C
780 lines
26 KiB
C
/*
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* Copyright (c) 2015 Linaro Ltd.
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* Copyright (c) 2015 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include "hisi_sas.h"
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#define DRV_NAME "hisi_sas_v1_hw"
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/* global registers need init*/
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#define DLVRY_QUEUE_ENABLE 0x0
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#define IOST_BASE_ADDR_LO 0x8
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#define IOST_BASE_ADDR_HI 0xc
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#define ITCT_BASE_ADDR_LO 0x10
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#define ITCT_BASE_ADDR_HI 0x14
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#define BROKEN_MSG_ADDR_LO 0x18
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#define BROKEN_MSG_ADDR_HI 0x1c
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#define PHY_CONTEXT 0x20
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#define PHY_STATE 0x24
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#define PHY_PORT_NUM_MA 0x28
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#define PORT_STATE 0x2c
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#define PHY_CONN_RATE 0x30
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#define HGC_TRANS_TASK_CNT_LIMIT 0x38
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#define AXI_AHB_CLK_CFG 0x3c
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#define HGC_SAS_TXFAIL_RETRY_CTRL 0x84
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#define HGC_GET_ITV_TIME 0x90
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#define DEVICE_MSG_WORK_MODE 0x94
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#define I_T_NEXUS_LOSS_TIME 0xa0
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#define BUS_INACTIVE_LIMIT_TIME 0xa8
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#define REJECT_TO_OPEN_LIMIT_TIME 0xac
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#define CFG_AGING_TIME 0xbc
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#define CFG_AGING_TIME_ITCT_REL_OFF 0
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#define CFG_AGING_TIME_ITCT_REL_MSK (0x1 << CFG_AGING_TIME_ITCT_REL_OFF)
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#define HGC_DFX_CFG2 0xc0
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#define FIS_LIST_BADDR_L 0xc4
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#define CFG_1US_TIMER_TRSH 0xcc
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#define CFG_SAS_CONFIG 0xd4
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#define HGC_IOST_ECC_ADDR 0x140
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#define HGC_IOST_ECC_ADDR_BAD_OFF 16
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#define HGC_IOST_ECC_ADDR_BAD_MSK (0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF)
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#define HGC_DQ_ECC_ADDR 0x144
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#define HGC_DQ_ECC_ADDR_BAD_OFF 16
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#define HGC_DQ_ECC_ADDR_BAD_MSK (0xfff << HGC_DQ_ECC_ADDR_BAD_OFF)
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#define HGC_INVLD_DQE_INFO 0x148
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#define HGC_INVLD_DQE_INFO_DQ_OFF 0
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#define HGC_INVLD_DQE_INFO_DQ_MSK (0xffff << HGC_INVLD_DQE_INFO_DQ_OFF)
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#define HGC_INVLD_DQE_INFO_TYPE_OFF 16
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#define HGC_INVLD_DQE_INFO_TYPE_MSK (0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF)
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#define HGC_INVLD_DQE_INFO_FORCE_OFF 17
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#define HGC_INVLD_DQE_INFO_FORCE_MSK (0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF)
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#define HGC_INVLD_DQE_INFO_PHY_OFF 18
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#define HGC_INVLD_DQE_INFO_PHY_MSK (0x1 << HGC_INVLD_DQE_INFO_PHY_OFF)
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#define HGC_INVLD_DQE_INFO_ABORT_OFF 19
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#define HGC_INVLD_DQE_INFO_ABORT_MSK (0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF)
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#define HGC_INVLD_DQE_INFO_IPTT_OF_OFF 20
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#define HGC_INVLD_DQE_INFO_IPTT_OF_MSK (0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF)
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#define HGC_INVLD_DQE_INFO_SSP_ERR_OFF 21
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#define HGC_INVLD_DQE_INFO_SSP_ERR_MSK (0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF)
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#define HGC_INVLD_DQE_INFO_OFL_OFF 22
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#define HGC_INVLD_DQE_INFO_OFL_MSK (0x1 << HGC_INVLD_DQE_INFO_OFL_OFF)
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#define HGC_ITCT_ECC_ADDR 0x150
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#define HGC_ITCT_ECC_ADDR_BAD_OFF 16
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#define HGC_ITCT_ECC_ADDR_BAD_MSK (0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF)
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#define HGC_AXI_FIFO_ERR_INFO 0x154
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#define INT_COAL_EN 0x1bc
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#define OQ_INT_COAL_TIME 0x1c0
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#define OQ_INT_COAL_CNT 0x1c4
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#define ENT_INT_COAL_TIME 0x1c8
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#define ENT_INT_COAL_CNT 0x1cc
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#define OQ_INT_SRC 0x1d0
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#define OQ_INT_SRC_MSK 0x1d4
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#define ENT_INT_SRC1 0x1d8
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#define ENT_INT_SRC2 0x1dc
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#define ENT_INT_SRC2_DQ_CFG_ERR_OFF 25
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#define ENT_INT_SRC2_DQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF)
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#define ENT_INT_SRC2_CQ_CFG_ERR_OFF 27
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#define ENT_INT_SRC2_CQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF)
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#define ENT_INT_SRC2_AXI_WRONG_INT_OFF 28
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#define ENT_INT_SRC2_AXI_WRONG_INT_MSK (0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF)
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#define ENT_INT_SRC2_AXI_OVERLF_INT_OFF 29
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#define ENT_INT_SRC2_AXI_OVERLF_INT_MSK (0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF)
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#define ENT_INT_SRC_MSK1 0x1e0
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#define ENT_INT_SRC_MSK2 0x1e4
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#define SAS_ECC_INTR 0x1e8
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#define SAS_ECC_INTR_DQ_ECC1B_OFF 0
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#define SAS_ECC_INTR_DQ_ECC1B_MSK (0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF)
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#define SAS_ECC_INTR_DQ_ECCBAD_OFF 1
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#define SAS_ECC_INTR_DQ_ECCBAD_MSK (0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF)
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#define SAS_ECC_INTR_IOST_ECC1B_OFF 2
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#define SAS_ECC_INTR_IOST_ECC1B_MSK (0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF)
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#define SAS_ECC_INTR_IOST_ECCBAD_OFF 3
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#define SAS_ECC_INTR_IOST_ECCBAD_MSK (0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF)
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#define SAS_ECC_INTR_ITCT_ECC1B_OFF 4
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#define SAS_ECC_INTR_ITCT_ECC1B_MSK (0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF)
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#define SAS_ECC_INTR_ITCT_ECCBAD_OFF 5
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#define SAS_ECC_INTR_ITCT_ECCBAD_MSK (0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF)
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#define SAS_ECC_INTR_MSK 0x1ec
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#define HGC_ERR_STAT_EN 0x238
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#define DLVRY_Q_0_BASE_ADDR_LO 0x260
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#define DLVRY_Q_0_BASE_ADDR_HI 0x264
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#define DLVRY_Q_0_DEPTH 0x268
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#define DLVRY_Q_0_WR_PTR 0x26c
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#define DLVRY_Q_0_RD_PTR 0x270
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#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
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#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
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#define COMPL_Q_0_DEPTH 0x4e8
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#define COMPL_Q_0_WR_PTR 0x4ec
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#define COMPL_Q_0_RD_PTR 0x4f0
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#define HGC_ECC_ERR 0x7d0
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/* phy registers need init */
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#define PORT_BASE (0x800)
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#define PHY_CFG (PORT_BASE + 0x0)
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#define PHY_CFG_ENA_OFF 0
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#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
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#define PHY_CFG_DC_OPT_OFF 2
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#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
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#define PROG_PHY_LINK_RATE (PORT_BASE + 0xc)
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#define PROG_PHY_LINK_RATE_MAX_OFF 0
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#define PROG_PHY_LINK_RATE_MAX_MSK (0xf << PROG_PHY_LINK_RATE_MAX_OFF)
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#define PROG_PHY_LINK_RATE_MIN_OFF 4
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#define PROG_PHY_LINK_RATE_MIN_MSK (0xf << PROG_PHY_LINK_RATE_MIN_OFF)
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#define PROG_PHY_LINK_RATE_OOB_OFF 8
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#define PROG_PHY_LINK_RATE_OOB_MSK (0xf << PROG_PHY_LINK_RATE_OOB_OFF)
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#define PHY_CTRL (PORT_BASE + 0x14)
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#define PHY_CTRL_RESET_OFF 0
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#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
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#define PHY_RATE_NEGO (PORT_BASE + 0x30)
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#define PHY_PCN (PORT_BASE + 0x44)
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#define SL_TOUT_CFG (PORT_BASE + 0x8c)
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#define SL_CONTROL (PORT_BASE + 0x94)
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#define SL_CONTROL_NOTIFY_EN_OFF 0
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#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
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#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
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#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
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#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
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#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
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#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
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#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
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#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
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#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
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#define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
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#define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
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#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
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#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
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#define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
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#define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
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#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
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#define DONE_RECEIVED_TIME (PORT_BASE + 0x12c)
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#define CON_CFG_DRIVER (PORT_BASE + 0x130)
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#define PHY_CONFIG2 (PORT_BASE + 0x1a8)
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#define PHY_CONFIG2_FORCE_TXDEEMPH_OFF 3
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#define PHY_CONFIG2_FORCE_TXDEEMPH_MSK (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF)
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#define PHY_CONFIG2_TX_TRAIN_COMP_OFF 24
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#define PHY_CONFIG2_TX_TRAIN_COMP_MSK (0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF)
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#define CHL_INT0 (PORT_BASE + 0x1b0)
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#define CHL_INT0_PHYCTRL_NOTRDY_OFF 0
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#define CHL_INT0_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF)
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#define CHL_INT0_SN_FAIL_NGR_OFF 2
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#define CHL_INT0_SN_FAIL_NGR_MSK (0x1 << CHL_INT0_SN_FAIL_NGR_OFF)
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#define CHL_INT0_DWS_LOST_OFF 4
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#define CHL_INT0_DWS_LOST_MSK (0x1 << CHL_INT0_DWS_LOST_OFF)
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#define CHL_INT0_SL_IDAF_FAIL_OFF 10
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#define CHL_INT0_SL_IDAF_FAIL_MSK (0x1 << CHL_INT0_SL_IDAF_FAIL_OFF)
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#define CHL_INT0_ID_TIMEOUT_OFF 11
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#define CHL_INT0_ID_TIMEOUT_MSK (0x1 << CHL_INT0_ID_TIMEOUT_OFF)
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#define CHL_INT0_SL_OPAF_FAIL_OFF 12
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#define CHL_INT0_SL_OPAF_FAIL_MSK (0x1 << CHL_INT0_SL_OPAF_FAIL_OFF)
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#define CHL_INT0_SL_PS_FAIL_OFF 21
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#define CHL_INT0_SL_PS_FAIL_MSK (0x1 << CHL_INT0_SL_PS_FAIL_OFF)
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#define CHL_INT1 (PORT_BASE + 0x1b4)
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#define CHL_INT2 (PORT_BASE + 0x1b8)
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#define CHL_INT2_SL_RX_BC_ACK_OFF 2
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#define CHL_INT2_SL_RX_BC_ACK_MSK (0x1 << CHL_INT2_SL_RX_BC_ACK_OFF)
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#define CHL_INT2_SL_PHY_ENA_OFF 6
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#define CHL_INT2_SL_PHY_ENA_MSK (0x1 << CHL_INT2_SL_PHY_ENA_OFF)
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#define CHL_INT0_MSK (PORT_BASE + 0x1bc)
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#define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF 0
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#define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF)
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#define CHL_INT1_MSK (PORT_BASE + 0x1c0)
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#define CHL_INT2_MSK (PORT_BASE + 0x1c4)
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#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
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#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
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#define DMA_TX_STATUS_BUSY_OFF 0
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#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
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#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
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#define DMA_RX_STATUS_BUSY_OFF 0
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#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
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#define AXI_CFG 0x5100
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#define RESET_VALUE 0x7ffff
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/* HW dma structures */
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/* Delivery queue header */
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/* dw0 */
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#define CMD_HDR_RESP_REPORT_OFF 5
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#define CMD_HDR_RESP_REPORT_MSK 0x20
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#define CMD_HDR_TLR_CTRL_OFF 6
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#define CMD_HDR_TLR_CTRL_MSK 0xc0
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#define CMD_HDR_PORT_OFF 17
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#define CMD_HDR_PORT_MSK 0xe0000
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#define CMD_HDR_PRIORITY_OFF 27
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#define CMD_HDR_PRIORITY_MSK 0x8000000
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#define CMD_HDR_MODE_OFF 28
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#define CMD_HDR_MODE_MSK 0x10000000
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#define CMD_HDR_CMD_OFF 29
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#define CMD_HDR_CMD_MSK 0xe0000000
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/* dw1 */
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#define CMD_HDR_VERIFY_DTL_OFF 10
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#define CMD_HDR_VERIFY_DTL_MSK 0x400
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#define CMD_HDR_SSP_FRAME_TYPE_OFF 13
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#define CMD_HDR_SSP_FRAME_TYPE_MSK 0xe000
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#define CMD_HDR_DEVICE_ID_OFF 16
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#define CMD_HDR_DEVICE_ID_MSK 0xffff0000
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/* dw2 */
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#define CMD_HDR_CFL_OFF 0
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#define CMD_HDR_CFL_MSK 0x1ff
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#define CMD_HDR_MRFL_OFF 15
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#define CMD_HDR_MRFL_MSK 0xff8000
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#define CMD_HDR_FIRST_BURST_OFF 25
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#define CMD_HDR_FIRST_BURST_MSK 0x2000000
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/* dw3 */
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#define CMD_HDR_IPTT_OFF 0
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#define CMD_HDR_IPTT_MSK 0xffff
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/* dw6 */
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#define CMD_HDR_DATA_SGL_LEN_OFF 16
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#define CMD_HDR_DATA_SGL_LEN_MSK 0xffff0000
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/* Completion header */
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#define CMPLT_HDR_IPTT_OFF 0
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#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
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#define CMPLT_HDR_CMD_CMPLT_OFF 17
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#define CMPLT_HDR_CMD_CMPLT_MSK (0x1 << CMPLT_HDR_CMD_CMPLT_OFF)
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#define CMPLT_HDR_ERR_RCRD_XFRD_OFF 18
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#define CMPLT_HDR_ERR_RCRD_XFRD_MSK (0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF)
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#define CMPLT_HDR_RSPNS_XFRD_OFF 19
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#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
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#define CMPLT_HDR_IO_CFG_ERR_OFF 27
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#define CMPLT_HDR_IO_CFG_ERR_MSK (0x1 << CMPLT_HDR_IO_CFG_ERR_OFF)
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/* ITCT header */
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/* qw0 */
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#define ITCT_HDR_DEV_TYPE_OFF 0
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#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
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#define ITCT_HDR_VALID_OFF 2
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#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
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#define ITCT_HDR_BREAK_REPLY_ENA_OFF 3
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#define ITCT_HDR_BREAK_REPLY_ENA_MSK (0x1 << ITCT_HDR_BREAK_REPLY_ENA_OFF)
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#define ITCT_HDR_AWT_CONTROL_OFF 4
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#define ITCT_HDR_AWT_CONTROL_MSK (0x1 << ITCT_HDR_AWT_CONTROL_OFF)
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#define ITCT_HDR_MAX_CONN_RATE_OFF 5
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#define ITCT_HDR_MAX_CONN_RATE_MSK (0xf << ITCT_HDR_MAX_CONN_RATE_OFF)
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#define ITCT_HDR_VALID_LINK_NUM_OFF 9
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#define ITCT_HDR_VALID_LINK_NUM_MSK (0xf << ITCT_HDR_VALID_LINK_NUM_OFF)
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#define ITCT_HDR_PORT_ID_OFF 13
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#define ITCT_HDR_PORT_ID_MSK (0x7 << ITCT_HDR_PORT_ID_OFF)
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#define ITCT_HDR_SMP_TIMEOUT_OFF 16
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#define ITCT_HDR_SMP_TIMEOUT_MSK (0xffff << ITCT_HDR_SMP_TIMEOUT_OFF)
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#define ITCT_HDR_MAX_BURST_BYTES_OFF 16
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#define ITCT_HDR_MAX_BURST_BYTES_MSK (0xffffffff << \
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ITCT_MAX_BURST_BYTES_OFF)
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/* qw1 */
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#define ITCT_HDR_MAX_SAS_ADDR_OFF 0
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#define ITCT_HDR_MAX_SAS_ADDR_MSK (0xffffffffffffffff << \
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ITCT_HDR_MAX_SAS_ADDR_OFF)
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/* qw2 */
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#define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF 0
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#define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK (0xffff << \
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ITCT_HDR_IT_NEXUS_LOSS_TL_OFF)
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#define ITCT_HDR_BUS_INACTIVE_TL_OFF 16
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#define ITCT_HDR_BUS_INACTIVE_TL_MSK (0xffff << \
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ITCT_HDR_BUS_INACTIVE_TL_OFF)
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#define ITCT_HDR_MAX_CONN_TL_OFF 32
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#define ITCT_HDR_MAX_CONN_TL_MSK (0xffff << \
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ITCT_HDR_MAX_CONN_TL_OFF)
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#define ITCT_HDR_REJ_OPEN_TL_OFF 48
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#define ITCT_HDR_REJ_OPEN_TL_MSK (0xffff << \
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ITCT_REJ_OPEN_TL_OFF)
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/* Err record header */
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#define ERR_HDR_DMA_TX_ERR_TYPE_OFF 0
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#define ERR_HDR_DMA_TX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF)
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#define ERR_HDR_DMA_RX_ERR_TYPE_OFF 16
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#define ERR_HDR_DMA_RX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF)
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struct hisi_sas_complete_v1_hdr {
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__le32 data;
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};
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enum {
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HISI_SAS_PHY_BCAST_ACK = 0,
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HISI_SAS_PHY_SL_PHY_ENABLED,
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HISI_SAS_PHY_INT_ABNORMAL,
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HISI_SAS_PHY_INT_NR
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};
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enum {
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DMA_TX_ERR_BASE = 0x0,
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DMA_RX_ERR_BASE = 0x100,
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TRANS_TX_FAIL_BASE = 0x200,
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TRANS_RX_FAIL_BASE = 0x300,
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/* dma tx */
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|
DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */
|
|
DMA_TX_DIF_APP_ERR, /* 0x1 */
|
|
DMA_TX_DIF_RPP_ERR, /* 0x2 */
|
|
DMA_TX_AXI_BUS_ERR, /* 0x3 */
|
|
DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */
|
|
DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */
|
|
DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */
|
|
DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */
|
|
DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */
|
|
DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */
|
|
|
|
/* dma rx */
|
|
DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */
|
|
DMA_RX_DIF_CRC_ERR, /* 0x101 */
|
|
DMA_RX_DIF_APP_ERR, /* 0x102 */
|
|
DMA_RX_DIF_RPP_ERR, /* 0x103 */
|
|
DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */
|
|
DMA_RX_AXI_BUS_ERR, /* 0x105 */
|
|
DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */
|
|
DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */
|
|
DMA_RX_DATA_OFFSET_ERR, /* 0x108 */
|
|
DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */
|
|
DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */
|
|
DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */
|
|
DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */
|
|
|
|
/* trans tx */
|
|
TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */
|
|
TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */
|
|
TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */
|
|
TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */
|
|
TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */
|
|
TRANS_TX_RSVD1_ERR, /* 0x205 */
|
|
TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */
|
|
TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */
|
|
TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */
|
|
TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */
|
|
TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */
|
|
TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */
|
|
TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */
|
|
TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */
|
|
TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */
|
|
TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */
|
|
TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */
|
|
TRANS_TX_RSVD2_ERR, /* 0x211 */
|
|
TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */
|
|
TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */
|
|
TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */
|
|
TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */
|
|
TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */
|
|
TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */
|
|
TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */
|
|
TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */
|
|
TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */
|
|
TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */
|
|
TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */
|
|
TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */
|
|
TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */
|
|
TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */
|
|
|
|
/* trans rx */
|
|
TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */
|
|
TRANS_RX_FRAME_DONE_ERR, /* 0x301 */
|
|
TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */
|
|
TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */
|
|
TRANS_RX_RSVD0_ERR, /* 0x304 */
|
|
TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */
|
|
TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */
|
|
TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */
|
|
TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */
|
|
TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */
|
|
TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */
|
|
TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */
|
|
TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */
|
|
TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */
|
|
TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */
|
|
TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */
|
|
TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */
|
|
TRANS_RX_BAD_HASH_ERR, /* 0x311 */
|
|
TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */
|
|
TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */
|
|
TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */
|
|
TRANS_RX_NO_BALANCE_ERR, /* 0x315 */
|
|
TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */
|
|
TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */
|
|
TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */
|
|
TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */
|
|
TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */
|
|
};
|
|
|
|
#define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS)
|
|
#define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES)
|
|
#define HISI_SAS_FATAL_INT_NR (2)
|
|
|
|
#define HISI_SAS_MAX_INT_NR \
|
|
(HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\
|
|
HISI_SAS_FATAL_INT_NR)
|
|
|
|
static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
|
|
{
|
|
void __iomem *regs = hisi_hba->regs + off;
|
|
|
|
return readl(regs);
|
|
}
|
|
|
|
static void hisi_sas_write32(struct hisi_hba *hisi_hba,
|
|
u32 off, u32 val)
|
|
{
|
|
void __iomem *regs = hisi_hba->regs + off;
|
|
|
|
writel(val, regs);
|
|
}
|
|
|
|
static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba,
|
|
int phy_no, u32 off, u32 val)
|
|
{
|
|
void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
|
|
|
|
writel(val, regs);
|
|
}
|
|
|
|
static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
|
|
int phy_no, u32 off)
|
|
{
|
|
void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
|
|
|
|
return readl(regs);
|
|
}
|
|
|
|
static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
|
|
{
|
|
u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
|
|
|
|
cfg &= ~PHY_CFG_DC_OPT_MSK;
|
|
cfg |= 1 << PHY_CFG_DC_OPT_OFF;
|
|
hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
|
|
}
|
|
|
|
static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
|
|
{
|
|
u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2);
|
|
|
|
cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK;
|
|
hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, cfg);
|
|
}
|
|
|
|
static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
|
|
{
|
|
struct sas_identify_frame identify_frame;
|
|
u32 *identify_buffer;
|
|
|
|
memset(&identify_frame, 0, sizeof(identify_frame));
|
|
identify_frame.dev_type = SAS_END_DEVICE;
|
|
identify_frame.frame_type = 0;
|
|
identify_frame._un1 = 1;
|
|
identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
|
|
identify_frame.target_bits = SAS_PROTOCOL_NONE;
|
|
memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
|
|
memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
|
|
identify_frame.phy_id = phy_no;
|
|
identify_buffer = (u32 *)(&identify_frame);
|
|
|
|
hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
|
|
__swab32(identify_buffer[0]));
|
|
hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
|
|
identify_buffer[2]);
|
|
hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
|
|
identify_buffer[1]);
|
|
hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
|
|
identify_buffer[4]);
|
|
hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
|
|
identify_buffer[3]);
|
|
hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
|
|
__swab32(identify_buffer[5]));
|
|
}
|
|
|
|
static void init_id_frame_v1_hw(struct hisi_hba *hisi_hba)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < hisi_hba->n_phy; i++)
|
|
config_id_frame_v1_hw(hisi_hba, i);
|
|
}
|
|
|
|
static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
|
|
{
|
|
int i;
|
|
unsigned long end_time;
|
|
u32 val;
|
|
struct device *dev = &hisi_hba->pdev->dev;
|
|
|
|
for (i = 0; i < hisi_hba->n_phy; i++) {
|
|
u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL);
|
|
|
|
phy_ctrl |= PHY_CTRL_RESET_MSK;
|
|
hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl);
|
|
}
|
|
msleep(1); /* It is safe to wait for 50us */
|
|
|
|
/* Ensure DMA tx & rx idle */
|
|
for (i = 0; i < hisi_hba->n_phy; i++) {
|
|
u32 dma_tx_status, dma_rx_status;
|
|
|
|
end_time = jiffies + msecs_to_jiffies(1000);
|
|
|
|
while (1) {
|
|
dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
|
|
DMA_TX_STATUS);
|
|
dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
|
|
DMA_RX_STATUS);
|
|
|
|
if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
|
|
!(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
|
|
break;
|
|
|
|
msleep(20);
|
|
if (time_after(jiffies, end_time))
|
|
return -EIO;
|
|
}
|
|
}
|
|
|
|
/* Ensure axi bus idle */
|
|
end_time = jiffies + msecs_to_jiffies(1000);
|
|
while (1) {
|
|
u32 axi_status =
|
|
hisi_sas_read32(hisi_hba, AXI_CFG);
|
|
|
|
if (axi_status == 0)
|
|
break;
|
|
|
|
msleep(20);
|
|
if (time_after(jiffies, end_time))
|
|
return -EIO;
|
|
}
|
|
|
|
/* Apply reset and disable clock */
|
|
/* clk disable reg is offset by +4 bytes from clk enable reg */
|
|
regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
|
|
RESET_VALUE);
|
|
regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
|
|
RESET_VALUE);
|
|
msleep(1);
|
|
regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
|
|
if (RESET_VALUE != (val & RESET_VALUE)) {
|
|
dev_err(dev, "Reset failed\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/* De-reset and enable clock */
|
|
/* deassert rst reg is offset by +4 bytes from assert reg */
|
|
regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
|
|
RESET_VALUE);
|
|
regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
|
|
RESET_VALUE);
|
|
msleep(1);
|
|
regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
|
|
if (val & RESET_VALUE) {
|
|
dev_err(dev, "De-reset failed\n");
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void init_reg_v1_hw(struct hisi_hba *hisi_hba)
|
|
{
|
|
int i;
|
|
|
|
/* Global registers init*/
|
|
hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
|
|
(u32)((1ULL << hisi_hba->queue_count) - 1));
|
|
hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, 0x11);
|
|
hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, 0x1);
|
|
hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff);
|
|
hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x401);
|
|
hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0x64);
|
|
hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
|
|
hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x64);
|
|
hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x2710);
|
|
hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, 0x1);
|
|
hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x7a12);
|
|
hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, 0x9c40);
|
|
hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, 0x2);
|
|
hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
|
|
hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x186a0);
|
|
hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 1);
|
|
hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
|
|
hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
|
|
hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffffffff);
|
|
hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, 0);
|
|
hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
|
|
hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0);
|
|
hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
|
|
hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0);
|
|
hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0);
|
|
hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 0x2);
|
|
hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, 0x22000000);
|
|
|
|
for (i = 0; i < hisi_hba->n_phy; i++) {
|
|
hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x88a);
|
|
hisi_sas_phy_write32(hisi_hba, i, PHY_CONFIG2, 0x7c080);
|
|
hisi_sas_phy_write32(hisi_hba, i, PHY_RATE_NEGO, 0x415ee00);
|
|
hisi_sas_phy_write32(hisi_hba, i, PHY_PCN, 0x80a80000);
|
|
hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
|
|
hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x0);
|
|
hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
|
|
hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0);
|
|
hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x13f0a);
|
|
hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 3);
|
|
hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 8);
|
|
}
|
|
|
|
for (i = 0; i < hisi_hba->queue_count; i++) {
|
|
/* Delivery queue */
|
|
hisi_sas_write32(hisi_hba,
|
|
DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
|
|
upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
|
|
|
|
hisi_sas_write32(hisi_hba,
|
|
DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
|
|
lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
|
|
|
|
hisi_sas_write32(hisi_hba,
|
|
DLVRY_Q_0_DEPTH + (i * 0x14),
|
|
HISI_SAS_QUEUE_SLOTS);
|
|
|
|
/* Completion queue */
|
|
hisi_sas_write32(hisi_hba,
|
|
COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
|
|
upper_32_bits(hisi_hba->complete_hdr_dma[i]));
|
|
|
|
hisi_sas_write32(hisi_hba,
|
|
COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
|
|
lower_32_bits(hisi_hba->complete_hdr_dma[i]));
|
|
|
|
hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
|
|
HISI_SAS_QUEUE_SLOTS);
|
|
}
|
|
|
|
/* itct */
|
|
hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
|
|
lower_32_bits(hisi_hba->itct_dma));
|
|
|
|
hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
|
|
upper_32_bits(hisi_hba->itct_dma));
|
|
|
|
/* iost */
|
|
hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
|
|
lower_32_bits(hisi_hba->iost_dma));
|
|
|
|
hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
|
|
upper_32_bits(hisi_hba->iost_dma));
|
|
|
|
/* breakpoint */
|
|
hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO,
|
|
lower_32_bits(hisi_hba->breakpoint_dma));
|
|
|
|
hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI,
|
|
upper_32_bits(hisi_hba->breakpoint_dma));
|
|
}
|
|
|
|
static int hw_init_v1_hw(struct hisi_hba *hisi_hba)
|
|
{
|
|
struct device *dev = &hisi_hba->pdev->dev;
|
|
int rc;
|
|
|
|
rc = reset_hw_v1_hw(hisi_hba);
|
|
if (rc) {
|
|
dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
|
|
return rc;
|
|
}
|
|
|
|
msleep(100);
|
|
init_reg_v1_hw(hisi_hba);
|
|
|
|
init_id_frame_v1_hw(hisi_hba);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
|
|
{
|
|
u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
|
|
|
|
cfg |= PHY_CFG_ENA_MSK;
|
|
hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
|
|
}
|
|
|
|
static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
|
|
{
|
|
config_id_frame_v1_hw(hisi_hba, phy_no);
|
|
config_phy_opt_mode_v1_hw(hisi_hba, phy_no);
|
|
config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no);
|
|
enable_phy_v1_hw(hisi_hba, phy_no);
|
|
}
|
|
|
|
static void start_phys_v1_hw(unsigned long data)
|
|
{
|
|
struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
|
|
int i;
|
|
|
|
for (i = 0; i < hisi_hba->n_phy; i++) {
|
|
hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a);
|
|
start_phy_v1_hw(hisi_hba, i);
|
|
}
|
|
}
|
|
|
|
static void phys_init_v1_hw(struct hisi_hba *hisi_hba)
|
|
{
|
|
int i;
|
|
struct timer_list *timer = &hisi_hba->timer;
|
|
|
|
for (i = 0; i < hisi_hba->n_phy; i++) {
|
|
hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
|
|
hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
|
|
}
|
|
|
|
setup_timer(timer, start_phys_v1_hw, (unsigned long)hisi_hba);
|
|
mod_timer(timer, jiffies + HZ);
|
|
}
|
|
|
|
static int hisi_sas_v1_init(struct hisi_hba *hisi_hba)
|
|
{
|
|
int rc;
|
|
|
|
rc = hw_init_v1_hw(hisi_hba);
|
|
if (rc)
|
|
return rc;
|
|
|
|
phys_init_v1_hw(hisi_hba);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct hisi_sas_hw hisi_sas_v1_hw = {
|
|
.hw_init = hisi_sas_v1_init,
|
|
.complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr),
|
|
};
|
|
|
|
static int hisi_sas_v1_probe(struct platform_device *pdev)
|
|
{
|
|
return hisi_sas_probe(pdev, &hisi_sas_v1_hw);
|
|
}
|
|
|
|
static int hisi_sas_v1_remove(struct platform_device *pdev)
|
|
{
|
|
return hisi_sas_remove(pdev);
|
|
}
|
|
|
|
static const struct of_device_id sas_v1_of_match[] = {
|
|
{ .compatible = "hisilicon,hip05-sas-v1",},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sas_v1_of_match);
|
|
|
|
static struct platform_driver hisi_sas_v1_driver = {
|
|
.probe = hisi_sas_v1_probe,
|
|
.remove = hisi_sas_v1_remove,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.of_match_table = sas_v1_of_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(hisi_sas_v1_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
|
|
MODULE_DESCRIPTION("HISILICON SAS controller v1 hw driver");
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|