forked from Minki/linux
d027db132b
This contains the bulk of new SoC development for this merge window. Two new platforms have been added, the sunxi platforms (Allwinner A1x SoCs) by Maxime Ripard, and a generic Broadcom platform for a new series of ARMv7 platforms from them, where the hope is that we can keep the platform code generic enough to have them all share one mach directory. The new Broadcom platform is contributed by Christian Daudt. Highbank has grown support for Calxeda's next generation of hardware, ECX-2000. clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also taken on maintainership of the platform. Beyond this there has been a bunch of work from a number of people on converting more platforms to IRQ domains, pinctrl conversion, cleanup and general feature enablement across most of the active platforms. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJQyLCjAAoJEIwa5zzehBx3AdQP/R+L3+EQMjiEWt/p7g/ql5Em 0SnP92CcGzrjgLTg9z1FeOazfOsGnkZAYUlDRkqfKobH3VqkhYFFtt1/0x0KMahm xcowHgMBOyimFdWT9vLK3J8U6DLui5XrEG9LGH2VL+lqmfjIyP/OOF3mVc0/+pV9 WTLAsYswdBRSeiNuF43kqlfrOwF6xsPLgiNMlc82w6BzHqoHu6dOif5M9MqWaApS V74DPmwLD371Tyit6aHqt3JOqpgiPSHlmxkzomK+5idcW3Pa7HnzzFYmx85dk/eN J2siqIkoOu7tEfjIbNZTL2MYoX4tUUKv4qZZ3IOl3YSWaV3P5ilMApF01XVrkk8E DWOMhzte9hC7L90W+/kCPLF1VyeAhCem2KQWUitO71fKur3r+3ZaUokNVvWzkJIL 7aduxAJOV2hfLgEqbjbjF3o4S8p63OV3kzivFJM1And15zDJo4+qqOh67+bPo4jj +R4du+SqzXriw4i3tDLGVpdjDffk4D41tbLzgkWAtvGyoP45yeYfHAzAh0pDFPRv ASfZVmZ5PhwAUAkIMnpC2sjgmxMYff3SYqmDgnsqXES7rbDH/hG+teymtHFTyUQp m+f60DNotSMcMvkLdvruLSB4aeTiwbfOqPn/g+aXYUlPuNMq1fVWgN7EJKWkamK4 nRwaJmLwx1/ojcVbpy2G =YMKB -----END PGP SIGNATURE----- Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC updates from Olof Johansson: "This contains the bulk of new SoC development for this merge window. Two new platforms have been added, the sunxi platforms (Allwinner A1x SoCs) by Maxime Ripard, and a generic Broadcom platform for a new series of ARMv7 platforms from them, where the hope is that we can keep the platform code generic enough to have them all share one mach directory. The new Broadcom platform is contributed by Christian Daudt. Highbank has grown support for Calxeda's next generation of hardware, ECX-2000. clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also taken on maintainership of the platform. Beyond this there has been a bunch of work from a number of people on converting more platforms to IRQ domains, pinctrl conversion, cleanup and general feature enablement across most of the active platforms." Fix up trivial conflicts as per Olof. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits) mfd: vexpress-sysreg: Remove LEDs code irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids irq: versatile: delete dangling variable ARM: sunxi: add missing include for mdelay() ARM: EXYNOS: Avoid early use of of_machine_is_compatible() ARM: dts: add node for PL330 MDMA1 controller for exynos4 ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412 ARM: EXYNOS: add UART3 to DEBUG_LL ports ARM: S3C24XX: Add clkdev entry for camif-upll clock ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers ARM: sunxi: Add missing sun4i.dtsi file pinctrl: samsung: Do not initialise statics to 0 ARM i.MX6: remove gate_mask from pllv3 ARM i.MX6: Fix ethernet PLL clocks ARM i.MX6: rename PLLs according to datasheet ARM i.MX6: Add pwm support ARM i.MX51: Add pwm support ARM i.MX53: Add pwm support ARM: mx5: Replace clk_register_clkdev with clock DT lookup ...
943 lines
22 KiB
C
943 lines
22 KiB
C
/*
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* TI DaVinci DM644x chip specific setup
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*
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* Author: Kevin Hilman, Deep Root Systems, LLC
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*
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* 2007 (c) Deep Root Systems, LLC. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/serial_8250.h>
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#include <linux/platform_device.h>
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#include <asm/mach/map.h>
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#include <mach/cputype.h>
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#include <mach/edma.h>
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#include <mach/irqs.h>
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#include <mach/psc.h>
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#include <mach/mux.h>
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#include <mach/time.h>
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#include <mach/serial.h>
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#include <mach/common.h>
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#include <mach/gpio-davinci.h>
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#include "davinci.h"
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#include "clock.h"
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#include "mux.h"
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#include "asp.h"
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/*
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* Device specific clocks
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*/
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#define DM644X_REF_FREQ 27000000
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#define DM644X_EMAC_BASE 0x01c80000
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#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
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#define DM644X_EMAC_CNTRL_OFFSET 0x0000
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#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
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#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
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#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
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static struct pll_data pll1_data = {
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.num = 1,
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.phys_base = DAVINCI_PLL1_BASE,
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};
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static struct pll_data pll2_data = {
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.num = 2,
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.phys_base = DAVINCI_PLL2_BASE,
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};
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static struct clk ref_clk = {
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.name = "ref_clk",
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.rate = DM644X_REF_FREQ,
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};
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static struct clk pll1_clk = {
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.name = "pll1",
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.parent = &ref_clk,
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.pll_data = &pll1_data,
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.flags = CLK_PLL,
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};
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static struct clk pll1_sysclk1 = {
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.name = "pll1_sysclk1",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk pll1_sysclk2 = {
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.name = "pll1_sysclk2",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV2,
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};
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static struct clk pll1_sysclk3 = {
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.name = "pll1_sysclk3",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV3,
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};
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static struct clk pll1_sysclk5 = {
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.name = "pll1_sysclk5",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV5,
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};
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static struct clk pll1_aux_clk = {
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.name = "pll1_aux_clk",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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};
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static struct clk pll1_sysclkbp = {
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.name = "pll1_sysclkbp",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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.div_reg = BPDIV
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};
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static struct clk pll2_clk = {
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.name = "pll2",
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.parent = &ref_clk,
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.pll_data = &pll2_data,
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.flags = CLK_PLL,
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};
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static struct clk pll2_sysclk1 = {
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.name = "pll2_sysclk1",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk pll2_sysclk2 = {
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.name = "pll2_sysclk2",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV2,
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};
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static struct clk pll2_sysclkbp = {
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.name = "pll2_sysclkbp",
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.parent = &pll2_clk,
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.flags = CLK_PLL | PRE_PLL,
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.div_reg = BPDIV
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};
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static struct clk dsp_clk = {
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.name = "dsp",
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.parent = &pll1_sysclk1,
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.lpsc = DAVINCI_LPSC_GEM,
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.domain = DAVINCI_GPSC_DSPDOMAIN,
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.usecount = 1, /* REVISIT how to disable? */
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};
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static struct clk arm_clk = {
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.name = "arm",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_ARM,
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.flags = ALWAYS_ENABLED,
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};
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static struct clk vicp_clk = {
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.name = "vicp",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_IMCOP,
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.domain = DAVINCI_GPSC_DSPDOMAIN,
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.usecount = 1, /* REVISIT how to disable? */
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};
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static struct clk vpss_master_clk = {
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.name = "vpss_master",
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.parent = &pll1_sysclk3,
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.lpsc = DAVINCI_LPSC_VPSSMSTR,
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.flags = CLK_PSC,
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};
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static struct clk vpss_slave_clk = {
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.name = "vpss_slave",
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.parent = &pll1_sysclk3,
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.lpsc = DAVINCI_LPSC_VPSSSLV,
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};
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static struct clk uart0_clk = {
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.name = "uart0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_UART0,
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};
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static struct clk uart1_clk = {
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.name = "uart1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_UART1,
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};
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static struct clk uart2_clk = {
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.name = "uart2",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_UART2,
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};
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static struct clk emac_clk = {
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.name = "emac",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
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};
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static struct clk i2c_clk = {
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.name = "i2c",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_I2C,
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};
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static struct clk ide_clk = {
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.name = "ide",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_ATA,
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};
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static struct clk asp_clk = {
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.name = "asp0",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_McBSP,
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};
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static struct clk mmcsd_clk = {
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.name = "mmcsd",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_MMC_SD,
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};
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static struct clk spi_clk = {
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.name = "spi",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_SPI,
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};
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static struct clk gpio_clk = {
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.name = "gpio",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_GPIO,
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};
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static struct clk usb_clk = {
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.name = "usb",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_USB,
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};
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static struct clk vlynq_clk = {
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.name = "vlynq",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_VLYNQ,
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};
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static struct clk aemif_clk = {
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.name = "aemif",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_AEMIF,
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};
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static struct clk pwm0_clk = {
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.name = "pwm0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM0,
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};
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static struct clk pwm1_clk = {
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.name = "pwm1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM1,
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};
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static struct clk pwm2_clk = {
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.name = "pwm2",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM2,
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};
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static struct clk timer0_clk = {
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.name = "timer0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER0,
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};
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static struct clk timer1_clk = {
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.name = "timer1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER1,
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};
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static struct clk timer2_clk = {
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.name = "timer2",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER2,
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.usecount = 1, /* REVISIT: why can't this be disabled? */
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};
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static struct clk_lookup dm644x_clks[] = {
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CLK(NULL, "ref", &ref_clk),
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CLK(NULL, "pll1", &pll1_clk),
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CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
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CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
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CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
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CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
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CLK(NULL, "pll1_aux", &pll1_aux_clk),
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CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
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CLK(NULL, "pll2", &pll2_clk),
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CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
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CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
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CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
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CLK(NULL, "dsp", &dsp_clk),
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CLK(NULL, "arm", &arm_clk),
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CLK(NULL, "vicp", &vicp_clk),
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CLK(NULL, "vpss_master", &vpss_master_clk),
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CLK(NULL, "vpss_slave", &vpss_slave_clk),
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CLK(NULL, "arm", &arm_clk),
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CLK(NULL, "uart0", &uart0_clk),
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CLK(NULL, "uart1", &uart1_clk),
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CLK(NULL, "uart2", &uart2_clk),
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CLK("davinci_emac.1", NULL, &emac_clk),
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CLK("i2c_davinci.1", NULL, &i2c_clk),
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CLK("palm_bk3710", NULL, &ide_clk),
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CLK("davinci-mcbsp", NULL, &asp_clk),
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CLK("davinci_mmc.0", NULL, &mmcsd_clk),
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CLK(NULL, "spi", &spi_clk),
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CLK(NULL, "gpio", &gpio_clk),
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CLK(NULL, "usb", &usb_clk),
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CLK(NULL, "vlynq", &vlynq_clk),
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CLK(NULL, "aemif", &aemif_clk),
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CLK(NULL, "pwm0", &pwm0_clk),
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CLK(NULL, "pwm1", &pwm1_clk),
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CLK(NULL, "pwm2", &pwm2_clk),
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CLK(NULL, "timer0", &timer0_clk),
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CLK(NULL, "timer1", &timer1_clk),
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CLK("watchdog", NULL, &timer2_clk),
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CLK(NULL, NULL, NULL),
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};
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static struct emac_platform_data dm644x_emac_pdata = {
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.ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
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.ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
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.ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
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.ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
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.version = EMAC_VERSION_1,
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};
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static struct resource dm644x_emac_resources[] = {
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{
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.start = DM644X_EMAC_BASE,
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.end = DM644X_EMAC_BASE + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_EMACINT,
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.end = IRQ_EMACINT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device dm644x_emac_device = {
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.name = "davinci_emac",
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.id = 1,
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.dev = {
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.platform_data = &dm644x_emac_pdata,
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},
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.num_resources = ARRAY_SIZE(dm644x_emac_resources),
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.resource = dm644x_emac_resources,
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};
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static struct resource dm644x_mdio_resources[] = {
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{
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.start = DM644X_EMAC_MDIO_BASE,
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.end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device dm644x_mdio_device = {
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.name = "davinci_mdio",
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.id = 0,
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.num_resources = ARRAY_SIZE(dm644x_mdio_resources),
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.resource = dm644x_mdio_resources,
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};
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/*
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* Device specific mux setup
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*
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* soc description mux mode mode mux dbg
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* reg offset mask mode
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*/
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static const struct mux_config dm644x_pins[] = {
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#ifdef CONFIG_DAVINCI_MUX
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MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
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MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
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MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
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MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
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MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
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MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
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MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
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MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
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MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
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MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
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MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
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MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
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MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
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MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
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MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
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MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
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MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
|
|
|
|
MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
|
|
|
|
MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
|
|
MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
|
|
MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
|
|
|
|
MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
|
|
|
|
MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
|
|
|
|
MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
|
|
MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
|
|
MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
|
|
MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
|
|
|
|
MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
|
|
|
|
MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
|
|
MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
|
|
#endif
|
|
};
|
|
|
|
/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
|
|
static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
|
|
[IRQ_VDINT0] = 2,
|
|
[IRQ_VDINT1] = 6,
|
|
[IRQ_VDINT2] = 6,
|
|
[IRQ_HISTINT] = 6,
|
|
[IRQ_H3AINT] = 6,
|
|
[IRQ_PRVUINT] = 6,
|
|
[IRQ_RSZINT] = 6,
|
|
[7] = 7,
|
|
[IRQ_VENCINT] = 6,
|
|
[IRQ_ASQINT] = 6,
|
|
[IRQ_IMXINT] = 6,
|
|
[IRQ_VLCDINT] = 6,
|
|
[IRQ_USBINT] = 4,
|
|
[IRQ_EMACINT] = 4,
|
|
[14] = 7,
|
|
[15] = 7,
|
|
[IRQ_CCINT0] = 5, /* dma */
|
|
[IRQ_CCERRINT] = 5, /* dma */
|
|
[IRQ_TCERRINT0] = 5, /* dma */
|
|
[IRQ_TCERRINT] = 5, /* dma */
|
|
[IRQ_PSCIN] = 7,
|
|
[21] = 7,
|
|
[IRQ_IDE] = 4,
|
|
[23] = 7,
|
|
[IRQ_MBXINT] = 7,
|
|
[IRQ_MBRINT] = 7,
|
|
[IRQ_MMCINT] = 7,
|
|
[IRQ_SDIOINT] = 7,
|
|
[28] = 7,
|
|
[IRQ_DDRINT] = 7,
|
|
[IRQ_AEMIFINT] = 7,
|
|
[IRQ_VLQINT] = 4,
|
|
[IRQ_TINT0_TINT12] = 2, /* clockevent */
|
|
[IRQ_TINT0_TINT34] = 2, /* clocksource */
|
|
[IRQ_TINT1_TINT12] = 7, /* DSP timer */
|
|
[IRQ_TINT1_TINT34] = 7, /* system tick */
|
|
[IRQ_PWMINT0] = 7,
|
|
[IRQ_PWMINT1] = 7,
|
|
[IRQ_PWMINT2] = 7,
|
|
[IRQ_I2C] = 3,
|
|
[IRQ_UARTINT0] = 3,
|
|
[IRQ_UARTINT1] = 3,
|
|
[IRQ_UARTINT2] = 3,
|
|
[IRQ_SPINT0] = 3,
|
|
[IRQ_SPINT1] = 3,
|
|
[45] = 7,
|
|
[IRQ_DSP2ARM0] = 4,
|
|
[IRQ_DSP2ARM1] = 4,
|
|
[IRQ_GPIO0] = 7,
|
|
[IRQ_GPIO1] = 7,
|
|
[IRQ_GPIO2] = 7,
|
|
[IRQ_GPIO3] = 7,
|
|
[IRQ_GPIO4] = 7,
|
|
[IRQ_GPIO5] = 7,
|
|
[IRQ_GPIO6] = 7,
|
|
[IRQ_GPIO7] = 7,
|
|
[IRQ_GPIOBNK0] = 7,
|
|
[IRQ_GPIOBNK1] = 7,
|
|
[IRQ_GPIOBNK2] = 7,
|
|
[IRQ_GPIOBNK3] = 7,
|
|
[IRQ_GPIOBNK4] = 7,
|
|
[IRQ_COMMTX] = 7,
|
|
[IRQ_COMMRX] = 7,
|
|
[IRQ_EMUINT] = 7,
|
|
};
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static const s8
|
|
queue_tc_mapping[][2] = {
|
|
/* {event queue no, TC no} */
|
|
{0, 0},
|
|
{1, 1},
|
|
{-1, -1},
|
|
};
|
|
|
|
static const s8
|
|
queue_priority_mapping[][2] = {
|
|
/* {event queue no, Priority} */
|
|
{0, 3},
|
|
{1, 7},
|
|
{-1, -1},
|
|
};
|
|
|
|
static struct edma_soc_info edma_cc0_info = {
|
|
.n_channel = 64,
|
|
.n_region = 4,
|
|
.n_slot = 128,
|
|
.n_tc = 2,
|
|
.n_cc = 1,
|
|
.queue_tc_mapping = queue_tc_mapping,
|
|
.queue_priority_mapping = queue_priority_mapping,
|
|
.default_queue = EVENTQ_1,
|
|
};
|
|
|
|
static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
|
|
&edma_cc0_info,
|
|
};
|
|
|
|
static struct resource edma_resources[] = {
|
|
{
|
|
.name = "edma_cc0",
|
|
.start = 0x01c00000,
|
|
.end = 0x01c00000 + SZ_64K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.name = "edma_tc0",
|
|
.start = 0x01c10000,
|
|
.end = 0x01c10000 + SZ_1K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.name = "edma_tc1",
|
|
.start = 0x01c10400,
|
|
.end = 0x01c10400 + SZ_1K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.name = "edma0",
|
|
.start = IRQ_CCINT0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.name = "edma0_err",
|
|
.start = IRQ_CCERRINT,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
/* not using TC*_ERR */
|
|
};
|
|
|
|
static struct platform_device dm644x_edma_device = {
|
|
.name = "edma",
|
|
.id = 0,
|
|
.dev.platform_data = dm644x_edma_info,
|
|
.num_resources = ARRAY_SIZE(edma_resources),
|
|
.resource = edma_resources,
|
|
};
|
|
|
|
/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
|
|
static struct resource dm644x_asp_resources[] = {
|
|
{
|
|
.start = DAVINCI_ASP0_BASE,
|
|
.end = DAVINCI_ASP0_BASE + SZ_8K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = DAVINCI_DMA_ASP0_TX,
|
|
.end = DAVINCI_DMA_ASP0_TX,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
{
|
|
.start = DAVINCI_DMA_ASP0_RX,
|
|
.end = DAVINCI_DMA_ASP0_RX,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dm644x_asp_device = {
|
|
.name = "davinci-mcbsp",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(dm644x_asp_resources),
|
|
.resource = dm644x_asp_resources,
|
|
};
|
|
|
|
#define DM644X_VPSS_BASE 0x01c73400
|
|
|
|
static struct resource dm644x_vpss_resources[] = {
|
|
{
|
|
/* VPSS Base address */
|
|
.name = "vpss",
|
|
.start = DM644X_VPSS_BASE,
|
|
.end = DM644X_VPSS_BASE + 0xff,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dm644x_vpss_device = {
|
|
.name = "vpss",
|
|
.id = -1,
|
|
.dev.platform_data = "dm644x_vpss",
|
|
.num_resources = ARRAY_SIZE(dm644x_vpss_resources),
|
|
.resource = dm644x_vpss_resources,
|
|
};
|
|
|
|
static struct resource dm644x_vpfe_resources[] = {
|
|
{
|
|
.start = IRQ_VDINT0,
|
|
.end = IRQ_VDINT0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = IRQ_VDINT1,
|
|
.end = IRQ_VDINT1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
|
|
static struct resource dm644x_ccdc_resource[] = {
|
|
/* CCDC Base address */
|
|
{
|
|
.start = 0x01c70400,
|
|
.end = 0x01c70400 + 0xff,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dm644x_ccdc_dev = {
|
|
.name = "dm644x_ccdc",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
|
|
.resource = dm644x_ccdc_resource,
|
|
.dev = {
|
|
.dma_mask = &dm644x_video_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
};
|
|
|
|
static struct platform_device dm644x_vpfe_dev = {
|
|
.name = CAPTURE_DRV_NAME,
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
|
|
.resource = dm644x_vpfe_resources,
|
|
.dev = {
|
|
.dma_mask = &dm644x_video_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
};
|
|
|
|
#define DM644X_OSD_BASE 0x01c72600
|
|
|
|
static struct resource dm644x_osd_resources[] = {
|
|
{
|
|
.start = DM644X_OSD_BASE,
|
|
.end = DM644X_OSD_BASE + 0x1ff,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct osd_platform_data dm644x_osd_data = {
|
|
.vpbe_type = VPBE_VERSION_1,
|
|
};
|
|
|
|
static struct platform_device dm644x_osd_dev = {
|
|
.name = VPBE_OSD_SUBDEV_NAME,
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(dm644x_osd_resources),
|
|
.resource = dm644x_osd_resources,
|
|
.dev = {
|
|
.dma_mask = &dm644x_video_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &dm644x_osd_data,
|
|
},
|
|
};
|
|
|
|
#define DM644X_VENC_BASE 0x01c72400
|
|
|
|
static struct resource dm644x_venc_resources[] = {
|
|
{
|
|
.start = DM644X_VENC_BASE,
|
|
.end = DM644X_VENC_BASE + 0x17f,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
#define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
|
|
#define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
|
|
#define DM644X_VPSS_VENCLKEN BIT(3)
|
|
#define DM644X_VPSS_DACCLKEN BIT(4)
|
|
|
|
static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
|
|
unsigned int pclock)
|
|
{
|
|
int ret = 0;
|
|
u32 v = DM644X_VPSS_VENCLKEN;
|
|
|
|
switch (type) {
|
|
case VPBE_ENC_STD:
|
|
v |= DM644X_VPSS_DACCLKEN;
|
|
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
|
|
break;
|
|
case VPBE_ENC_CUSTOM_TIMINGS:
|
|
if (pclock <= 27000000) {
|
|
v |= DM644X_VPSS_DACCLKEN;
|
|
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
|
|
} else {
|
|
/*
|
|
* For HD, use external clock source since
|
|
* HD requires higher clock rate
|
|
*/
|
|
v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
|
|
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
|
|
}
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct resource dm644x_v4l2_disp_resources[] = {
|
|
{
|
|
.start = IRQ_VENCINT,
|
|
.end = IRQ_VENCINT,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dm644x_vpbe_display = {
|
|
.name = "vpbe-v4l2",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
|
|
.resource = dm644x_v4l2_disp_resources,
|
|
.dev = {
|
|
.dma_mask = &dm644x_video_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
};
|
|
|
|
static struct venc_platform_data dm644x_venc_pdata = {
|
|
.venc_type = VPBE_VERSION_1,
|
|
.setup_clock = dm644x_venc_setup_clock,
|
|
};
|
|
|
|
static struct platform_device dm644x_venc_dev = {
|
|
.name = VPBE_VENC_SUBDEV_NAME,
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(dm644x_venc_resources),
|
|
.resource = dm644x_venc_resources,
|
|
.dev = {
|
|
.dma_mask = &dm644x_video_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &dm644x_venc_pdata,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dm644x_vpbe_dev = {
|
|
.name = "vpbe_controller",
|
|
.id = -1,
|
|
.dev = {
|
|
.dma_mask = &dm644x_video_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
};
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static struct map_desc dm644x_io_desc[] = {
|
|
{
|
|
.virtual = IO_VIRT,
|
|
.pfn = __phys_to_pfn(IO_PHYS),
|
|
.length = IO_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
|
|
/* Contents of JTAG ID register used to identify exact cpu type */
|
|
static struct davinci_id dm644x_ids[] = {
|
|
{
|
|
.variant = 0x0,
|
|
.part_no = 0xb700,
|
|
.manufacturer = 0x017,
|
|
.cpu_id = DAVINCI_CPU_ID_DM6446,
|
|
.name = "dm6446",
|
|
},
|
|
{
|
|
.variant = 0x1,
|
|
.part_no = 0xb700,
|
|
.manufacturer = 0x017,
|
|
.cpu_id = DAVINCI_CPU_ID_DM6446,
|
|
.name = "dm6446a",
|
|
},
|
|
};
|
|
|
|
static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
|
|
|
|
/*
|
|
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
|
|
* T0_TOP: Timer 0, top : clocksource for generic timekeeping
|
|
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
|
|
* T1_TOP: Timer 1, top : <unused>
|
|
*/
|
|
static struct davinci_timer_info dm644x_timer_info = {
|
|
.timers = davinci_timer_instance,
|
|
.clockevent_id = T0_BOT,
|
|
.clocksource_id = T0_TOP,
|
|
};
|
|
|
|
static struct plat_serial8250_port dm644x_serial_platform_data[] = {
|
|
{
|
|
.mapbase = DAVINCI_UART0_BASE,
|
|
.irq = IRQ_UARTINT0,
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
|
UPF_IOREMAP,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
},
|
|
{
|
|
.mapbase = DAVINCI_UART1_BASE,
|
|
.irq = IRQ_UARTINT1,
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
|
UPF_IOREMAP,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
},
|
|
{
|
|
.mapbase = DAVINCI_UART2_BASE,
|
|
.irq = IRQ_UARTINT2,
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
|
UPF_IOREMAP,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
},
|
|
{
|
|
.flags = 0
|
|
},
|
|
};
|
|
|
|
static struct platform_device dm644x_serial_device = {
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM,
|
|
.dev = {
|
|
.platform_data = dm644x_serial_platform_data,
|
|
},
|
|
};
|
|
|
|
static struct davinci_soc_info davinci_soc_info_dm644x = {
|
|
.io_desc = dm644x_io_desc,
|
|
.io_desc_num = ARRAY_SIZE(dm644x_io_desc),
|
|
.jtag_id_reg = 0x01c40028,
|
|
.ids = dm644x_ids,
|
|
.ids_num = ARRAY_SIZE(dm644x_ids),
|
|
.cpu_clks = dm644x_clks,
|
|
.psc_bases = dm644x_psc_bases,
|
|
.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
|
|
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
|
|
.pinmux_pins = dm644x_pins,
|
|
.pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
|
|
.intc_base = DAVINCI_ARM_INTC_BASE,
|
|
.intc_type = DAVINCI_INTC_TYPE_AINTC,
|
|
.intc_irq_prios = dm644x_default_priorities,
|
|
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
|
|
.timer_info = &dm644x_timer_info,
|
|
.gpio_type = GPIO_TYPE_DAVINCI,
|
|
.gpio_base = DAVINCI_GPIO_BASE,
|
|
.gpio_num = 71,
|
|
.gpio_irq = IRQ_GPIOBNK0,
|
|
.serial_dev = &dm644x_serial_device,
|
|
.emac_pdata = &dm644x_emac_pdata,
|
|
.sram_dma = 0x00008000,
|
|
.sram_len = SZ_16K,
|
|
};
|
|
|
|
void __init dm644x_init_asp(struct snd_platform_data *pdata)
|
|
{
|
|
davinci_cfg_reg(DM644X_MCBSP);
|
|
dm644x_asp_device.dev.platform_data = pdata;
|
|
platform_device_register(&dm644x_asp_device);
|
|
}
|
|
|
|
void __init dm644x_init(void)
|
|
{
|
|
davinci_common_init(&davinci_soc_info_dm644x);
|
|
davinci_map_sysmod();
|
|
}
|
|
|
|
int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
|
|
struct vpbe_config *vpbe_cfg)
|
|
{
|
|
if (vpfe_cfg || vpbe_cfg)
|
|
platform_device_register(&dm644x_vpss_device);
|
|
|
|
if (vpfe_cfg) {
|
|
dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
|
|
platform_device_register(&dm644x_ccdc_dev);
|
|
platform_device_register(&dm644x_vpfe_dev);
|
|
/* Add ccdc clock aliases */
|
|
clk_add_alias("master", dm644x_ccdc_dev.name,
|
|
"vpss_master", NULL);
|
|
clk_add_alias("slave", dm644x_ccdc_dev.name,
|
|
"vpss_slave", NULL);
|
|
}
|
|
|
|
if (vpbe_cfg) {
|
|
dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
|
|
platform_device_register(&dm644x_osd_dev);
|
|
platform_device_register(&dm644x_venc_dev);
|
|
platform_device_register(&dm644x_vpbe_dev);
|
|
platform_device_register(&dm644x_vpbe_display);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init dm644x_init_devices(void)
|
|
{
|
|
if (!cpu_is_davinci_dm644x())
|
|
return 0;
|
|
|
|
platform_device_register(&dm644x_edma_device);
|
|
|
|
platform_device_register(&dm644x_mdio_device);
|
|
platform_device_register(&dm644x_emac_device);
|
|
clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
|
|
NULL, &dm644x_emac_device.dev);
|
|
|
|
return 0;
|
|
}
|
|
postcore_initcall(dm644x_init_devices);
|