Vidya Sagar de60266825 phy: tegra: Add PCIe PIPE2UPHY support for Tegra234 ... Synopsys DesignWare core based PCIe controllers in Tegra234 SoC interface with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module. For each PCIe lane of a controller, there is a P2U unit instantiated at hardware level. This driver provides support for the programming required for each P2U that is going to be used for a PCIe controller. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Link: https://lore.kernel.org/r/20220629060435.25297-9-vidyas@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2022-07-05 11:44:35 +05:30
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Kconfig	phy: tegra: Select USB_COMMON for usb_get_maximum_speed()	2020-04-16 15:05:53 +02:00
Makefile	phy: tegra: xusb: Add Tegra194 support	2020-03-19 13:59:46 +01:00
phy-tegra194-p2u.c	phy: tegra: Add PCIe PIPE2UPHY support for Tegra234	2022-07-05 11:44:35 +05:30
xusb-tegra124.c	phy: tegra: Don't use device-managed API to allocate ports	2020-03-19 14:00:05 +01:00
xusb-tegra186.c	phy: tegra: xusb: Add wake/sleepwalk for Tegra186	2021-06-03 14:52:45 +02:00
xusb-tegra210.c	phy: tegra: xusb: Tegra210 host mode VBUS control	2021-06-03 14:52:45 +02:00
xusb.c	phy: tegra: xusb: Fix return value of tegra_xusb_find_port_node function	2021-12-14 13:07:21 +05:30
xusb.h	phy: tegra: xusb: Add sleepwalk and suspend/resume	2021-06-03 14:49:34 +02:00