forked from Minki/linux
f6c365fad1
TSE PCS SGMII ethernet has an issue where switching speed doesn't work caused by a faulty register macro offset. This fixes the issue. Signed-off-by: Jia Jie Ho <ho.jia.jie@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
275 lines
8.4 KiB
C
275 lines
8.4 KiB
C
/* Copyright Altera Corporation (C) 2016. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2,
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Author: Tien Hock Loh <thloh@altera.com>
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_net.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/stmmac.h>
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#include "stmmac.h"
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#include "stmmac_platform.h"
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#include "altr_tse_pcs.h"
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII BIT(1)
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII BIT(2)
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK GENMASK(1, 0)
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#define TSE_PCS_CONTROL_AN_EN_MASK BIT(12)
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#define TSE_PCS_CONTROL_REG 0x00
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#define TSE_PCS_CONTROL_RESTART_AN_MASK BIT(9)
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#define TSE_PCS_IF_MODE_REG 0x28
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#define TSE_PCS_LINK_TIMER_0_REG 0x24
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#define TSE_PCS_LINK_TIMER_1_REG 0x26
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#define TSE_PCS_SIZE 0x40
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#define TSE_PCS_STATUS_AN_COMPLETED_MASK BIT(5)
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#define TSE_PCS_STATUS_LINK_MASK 0x0004
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#define TSE_PCS_STATUS_REG 0x02
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#define TSE_PCS_SGMII_SPEED_1000 BIT(3)
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#define TSE_PCS_SGMII_SPEED_100 BIT(2)
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#define TSE_PCS_SGMII_SPEED_10 0x0
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#define TSE_PCS_SW_RST_MASK 0x8000
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#define TSE_PCS_PARTNER_ABILITY_REG 0x0A
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#define TSE_PCS_PARTNER_DUPLEX_FULL 0x1000
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#define TSE_PCS_PARTNER_DUPLEX_HALF 0x0000
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#define TSE_PCS_PARTNER_DUPLEX_MASK 0x1000
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#define TSE_PCS_PARTNER_SPEED_MASK GENMASK(11, 10)
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#define TSE_PCS_PARTNER_SPEED_1000 BIT(11)
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#define TSE_PCS_PARTNER_SPEED_100 BIT(10)
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#define TSE_PCS_PARTNER_SPEED_10 0x0000
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#define TSE_PCS_PARTNER_SPEED_1000 BIT(11)
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#define TSE_PCS_PARTNER_SPEED_100 BIT(10)
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#define TSE_PCS_PARTNER_SPEED_10 0x0000
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#define TSE_PCS_SGMII_SPEED_MASK GENMASK(3, 2)
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#define TSE_PCS_SGMII_LINK_TIMER_0 0x0D40
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#define TSE_PCS_SGMII_LINK_TIMER_1 0x0003
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#define TSE_PCS_SW_RESET_TIMEOUT 100
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#define TSE_PCS_USE_SGMII_AN_MASK BIT(1)
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#define TSE_PCS_USE_SGMII_ENA BIT(0)
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#define SGMII_ADAPTER_CTRL_REG 0x00
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#define SGMII_ADAPTER_DISABLE 0x0001
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#define SGMII_ADAPTER_ENABLE 0x0000
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#define AUTONEGO_LINK_TIMER 20
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static int tse_pcs_reset(void __iomem *base, struct tse_pcs *pcs)
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{
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int counter = 0;
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u16 val;
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val = readw(base + TSE_PCS_CONTROL_REG);
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val |= TSE_PCS_SW_RST_MASK;
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writew(val, base + TSE_PCS_CONTROL_REG);
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while (counter < TSE_PCS_SW_RESET_TIMEOUT) {
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val = readw(base + TSE_PCS_CONTROL_REG);
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val &= TSE_PCS_SW_RST_MASK;
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if (val == 0)
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break;
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counter++;
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udelay(1);
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}
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if (counter >= TSE_PCS_SW_RESET_TIMEOUT) {
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dev_err(pcs->dev, "PCS could not get out of sw reset\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs)
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{
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int ret = 0;
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writew(TSE_PCS_USE_SGMII_ENA, base + TSE_PCS_IF_MODE_REG);
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writew(TSE_PCS_SGMII_LINK_TIMER_0, base + TSE_PCS_LINK_TIMER_0_REG);
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writew(TSE_PCS_SGMII_LINK_TIMER_1, base + TSE_PCS_LINK_TIMER_1_REG);
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ret = tse_pcs_reset(base, pcs);
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if (ret == 0)
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writew(SGMII_ADAPTER_ENABLE,
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pcs->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
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return ret;
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}
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static void pcs_link_timer_callback(unsigned long data)
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{
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u16 val = 0;
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struct tse_pcs *pcs = (struct tse_pcs *)data;
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void __iomem *tse_pcs_base = pcs->tse_pcs_base;
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void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base;
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val = readw(tse_pcs_base + TSE_PCS_STATUS_REG);
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val &= TSE_PCS_STATUS_LINK_MASK;
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if (val != 0) {
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dev_dbg(pcs->dev, "Adapter: Link is established\n");
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writew(SGMII_ADAPTER_ENABLE,
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sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
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} else {
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mod_timer(&pcs->aneg_link_timer, jiffies +
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msecs_to_jiffies(AUTONEGO_LINK_TIMER));
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}
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}
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static void auto_nego_timer_callback(unsigned long data)
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{
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u16 val = 0;
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u16 speed = 0;
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u16 duplex = 0;
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struct tse_pcs *pcs = (struct tse_pcs *)data;
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void __iomem *tse_pcs_base = pcs->tse_pcs_base;
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void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base;
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val = readw(tse_pcs_base + TSE_PCS_STATUS_REG);
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val &= TSE_PCS_STATUS_AN_COMPLETED_MASK;
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if (val != 0) {
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dev_dbg(pcs->dev, "Adapter: Auto Negotiation is completed\n");
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val = readw(tse_pcs_base + TSE_PCS_PARTNER_ABILITY_REG);
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speed = val & TSE_PCS_PARTNER_SPEED_MASK;
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duplex = val & TSE_PCS_PARTNER_DUPLEX_MASK;
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if (speed == TSE_PCS_PARTNER_SPEED_10 &&
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duplex == TSE_PCS_PARTNER_DUPLEX_FULL)
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dev_dbg(pcs->dev,
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"Adapter: Link Partner is Up - 10/Full\n");
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else if (speed == TSE_PCS_PARTNER_SPEED_100 &&
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duplex == TSE_PCS_PARTNER_DUPLEX_FULL)
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dev_dbg(pcs->dev,
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"Adapter: Link Partner is Up - 100/Full\n");
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else if (speed == TSE_PCS_PARTNER_SPEED_1000 &&
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duplex == TSE_PCS_PARTNER_DUPLEX_FULL)
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dev_dbg(pcs->dev,
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"Adapter: Link Partner is Up - 1000/Full\n");
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else if (speed == TSE_PCS_PARTNER_SPEED_10 &&
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duplex == TSE_PCS_PARTNER_DUPLEX_HALF)
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dev_err(pcs->dev,
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"Adapter does not support Half Duplex\n");
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else if (speed == TSE_PCS_PARTNER_SPEED_100 &&
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duplex == TSE_PCS_PARTNER_DUPLEX_HALF)
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dev_err(pcs->dev,
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"Adapter does not support Half Duplex\n");
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else if (speed == TSE_PCS_PARTNER_SPEED_1000 &&
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duplex == TSE_PCS_PARTNER_DUPLEX_HALF)
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dev_err(pcs->dev,
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"Adapter does not support Half Duplex\n");
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else
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dev_err(pcs->dev,
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"Adapter: Invalid Partner Speed and Duplex\n");
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if (duplex == TSE_PCS_PARTNER_DUPLEX_FULL &&
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(speed == TSE_PCS_PARTNER_SPEED_10 ||
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speed == TSE_PCS_PARTNER_SPEED_100 ||
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speed == TSE_PCS_PARTNER_SPEED_1000))
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writew(SGMII_ADAPTER_ENABLE,
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sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
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} else {
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val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);
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val |= TSE_PCS_CONTROL_RESTART_AN_MASK;
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writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG);
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tse_pcs_reset(tse_pcs_base, pcs);
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mod_timer(&pcs->aneg_link_timer, jiffies +
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msecs_to_jiffies(AUTONEGO_LINK_TIMER));
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}
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}
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static void aneg_link_timer_callback(unsigned long data)
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{
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struct tse_pcs *pcs = (struct tse_pcs *)data;
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if (pcs->autoneg == AUTONEG_ENABLE)
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auto_nego_timer_callback(data);
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else if (pcs->autoneg == AUTONEG_DISABLE)
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pcs_link_timer_callback(data);
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}
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void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev,
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unsigned int speed)
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{
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void __iomem *tse_pcs_base = pcs->tse_pcs_base;
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void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base;
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u32 val;
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writew(SGMII_ADAPTER_ENABLE,
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sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
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pcs->autoneg = phy_dev->autoneg;
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if (phy_dev->autoneg == AUTONEG_ENABLE) {
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val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);
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val |= TSE_PCS_CONTROL_AN_EN_MASK;
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writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG);
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val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG);
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val |= TSE_PCS_USE_SGMII_AN_MASK;
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writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG);
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val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);
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val |= TSE_PCS_CONTROL_RESTART_AN_MASK;
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tse_pcs_reset(tse_pcs_base, pcs);
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setup_timer(&pcs->aneg_link_timer,
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aneg_link_timer_callback, (unsigned long)pcs);
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mod_timer(&pcs->aneg_link_timer, jiffies +
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msecs_to_jiffies(AUTONEGO_LINK_TIMER));
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} else if (phy_dev->autoneg == AUTONEG_DISABLE) {
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val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);
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val &= ~TSE_PCS_CONTROL_AN_EN_MASK;
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writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG);
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val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG);
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val &= ~TSE_PCS_USE_SGMII_AN_MASK;
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writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG);
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val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG);
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val &= ~TSE_PCS_SGMII_SPEED_MASK;
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switch (speed) {
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case 1000:
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val |= TSE_PCS_SGMII_SPEED_1000;
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break;
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case 100:
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val |= TSE_PCS_SGMII_SPEED_100;
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break;
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case 10:
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val |= TSE_PCS_SGMII_SPEED_10;
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break;
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default:
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return;
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}
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writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG);
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tse_pcs_reset(tse_pcs_base, pcs);
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setup_timer(&pcs->aneg_link_timer,
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aneg_link_timer_callback, (unsigned long)pcs);
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mod_timer(&pcs->aneg_link_timer, jiffies +
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msecs_to_jiffies(AUTONEGO_LINK_TIMER));
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}
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}
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