Ralf Baechle 44eeab6741 MIPS: Hibernation: Remove SMP TLB and cacheflushing code. ... We can't perform any flushes on SMP from swsusp_arch_resume because interrupts are disabled. A cross-CPU flush is unnecessary anyway because all but the local CPU have already been disabled. A local flush is not needed either because we didn't change any mappings. So just delete the code. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2009-06-24 18:34:39 +01:00
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cpu.c
hibernate.S	MIPS: Hibernation: Remove SMP TLB and cacheflushing code.	2009-06-24 18:34:39 +01:00
Makefile