forked from Minki/linux
8e781f6542
Cortex-A12 implements Performance Monitors compliant with the PMUv2 architecture. This patch adds support for the Cortex-A12 PMU to the ARM perf backend. Signed-off-by: Albin Tonnerre <albin.tonnerre@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
35 lines
897 B
Plaintext
35 lines
897 B
Plaintext
* ARM Performance Monitor Units
|
|
|
|
ARM cores often have a PMU for counting cpu and cache events like cache misses
|
|
and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
|
|
representation in the device tree should be done as under:-
|
|
|
|
Required properties:
|
|
|
|
- compatible : should be one of
|
|
"arm,armv8-pmuv3"
|
|
"arm,cortex-a15-pmu"
|
|
"arm,cortex-a12-pmu"
|
|
"arm,cortex-a9-pmu"
|
|
"arm,cortex-a8-pmu"
|
|
"arm,cortex-a7-pmu"
|
|
"arm,cortex-a5-pmu"
|
|
"arm,arm11mpcore-pmu"
|
|
"arm,arm1176-pmu"
|
|
"arm,arm1136-pmu"
|
|
"qcom,krait-pmu"
|
|
- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
|
|
interrupt (PPI) then 1 interrupt should be specified.
|
|
|
|
Optional properties:
|
|
|
|
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
|
|
events.
|
|
|
|
Example:
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a9-pmu";
|
|
interrupts = <100 101>;
|
|
};
|