forked from Minki/linux
8e6cb470ba
The driver never calls platform_set_drvdata() , so platform_get_drvdata() in .remove returns NULL and thus $indio_dev variable in .remove is NULL. Then it's only a matter of dereferencing the indio_dev variable to make the kernel blow as seen below. This patch adds the platform_set_drvdata() call to fix the problem. root@armhf:~# rmmod at91-sama5d2_adc Unable to handle kernel NULL pointer dereference at virtual address 000001d4 pgd = dd57c000 [000001d4] *pgd=00000000 Internal error: Oops: 5 [#1] ARM Modules linked in: at91_sama5d2_adc(-) CPU: 0 PID: 1334 Comm: rmmod Not tainted 4.6.0-rc3-next-20160418+ #3 Hardware name: Atmel SAMA5 task: dd4fcc40 ti: de910000 task.ti: de910000 PC is at mutex_lock+0x4/0x24 LR is at iio_device_unregister+0x14/0x6c pc : [<c05f4624>] lr : [<c0471f74>] psr: a00d0013 sp : de911f00 ip : 00000000 fp : be898bd8 r10: 00000000 r9 : de910000 r8 : c0107724 r7 : 00000081 r6 : bf001048 r5 : 000001d4 r4 : 00000000 r3 : bf000000 r2 : 00000000 r1 : 00000004 r0 : 000001d4 Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none Control: 10c53c7d Table: 3d57c059 DAC: 00000051 Process rmmod (pid: 1334, stack limit = 0xde910208) Stack: (0xde911f00 to 0xde912000) 1f00: bf000000 00000000 df5c7e10 bf000010 bf000000 df5c7e10 df5c7e10 c0351ca8 1f20: c0351c84 df5c7e10 bf001048 c0350734 bf001048 df5c7e10 df5c7e44 c035087c 1f40: bf001048 7f62dd4c 00000800 c034fb30 bf0010c0 c0158ee8 de910000 31397461 1f60: 6d61735f 32643561 6364615f 00000000 de911f90 de910000 de910000 00000000 1f80: de911fb0 10c53c7d de911f9c c05f33d8 de911fa0 00910000 be898ecb 7f62dd10 1fa0: 00000000 c0107560 be898ecb 7f62dd10 7f62dd4c 00000800 6f844800 6f844800 1fc0: be898ecb 7f62dd10 00000000 00000081 00000000 7f62dd10 be898bd8 be898bd8 1fe0: b6eedab1 be898b6c 7f61056b b6eedab6 000d0030 7f62dd4c 00000000 00000000 [<c05f4624>] (mutex_lock) from [<c0471f74>] (iio_device_unregister+0x14/0x6c) [<c0471f74>] (iio_device_unregister) from [<bf000010>] (at91_adc_remove+0x10/0x3c [at91_sama5d2_adc]) [<bf000010>] (at91_adc_remove [at91_sama5d2_adc]) from [<c0351ca8>] (platform_drv_remove+0x24/0x3c) [<c0351ca8>] (platform_drv_remove) from [<c0350734>] (__device_release_driver+0x84/0x110) [<c0350734>] (__device_release_driver) from [<c035087c>] (driver_detach+0x8c/0x90) [<c035087c>] (driver_detach) from [<c034fb30>] (bus_remove_driver+0x4c/0xa0) [<c034fb30>] (bus_remove_driver) from [<c0158ee8>] (SyS_delete_module+0x110/0x1d0) [<c0158ee8>] (SyS_delete_module) from [<c0107560>] (ret_fast_syscall+0x0/0x3c) Code: e3520001 1affffd5 eafffff4 f5d0f000 (e1902f9f) ---[ end trace 86914d7ad3696fca ]--- Signed-off-by: Marek Vasut <marex@denx.de> Cc: Ludovic Desroches <ludovic.desroches@atmel.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
511 lines
13 KiB
C
511 lines
13 KiB
C
/*
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* Atmel ADC driver for SAMA5D2 devices and compatible.
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*
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* Copyright (C) 2015 Atmel,
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* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/wait.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/regulator/consumer.h>
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/* Control Register */
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#define AT91_SAMA5D2_CR 0x00
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/* Software Reset */
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#define AT91_SAMA5D2_CR_SWRST BIT(0)
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/* Start Conversion */
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#define AT91_SAMA5D2_CR_START BIT(1)
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/* Touchscreen Calibration */
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#define AT91_SAMA5D2_CR_TSCALIB BIT(2)
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/* Comparison Restart */
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#define AT91_SAMA5D2_CR_CMPRST BIT(4)
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/* Mode Register */
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#define AT91_SAMA5D2_MR 0x04
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/* Trigger Selection */
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#define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1)
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/* ADTRG */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0
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/* TIOA0 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1
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/* TIOA1 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2
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/* TIOA2 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3
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/* PWM event line 0 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4
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/* PWM event line 1 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5
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/* TIOA3 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6
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/* RTCOUT0 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7
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/* Sleep Mode */
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#define AT91_SAMA5D2_MR_SLEEP BIT(5)
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/* Fast Wake Up */
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#define AT91_SAMA5D2_MR_FWUP BIT(6)
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/* Prescaler Rate Selection */
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#define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
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#define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8
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#define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff
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/* Startup Time */
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#define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16)
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/* Analog Change */
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#define AT91_SAMA5D2_MR_ANACH BIT(23)
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/* Tracking Time */
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#define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
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#define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff
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/* Transfer Time */
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#define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
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#define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3
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/* Use Sequence Enable */
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#define AT91_SAMA5D2_MR_USEQ BIT(31)
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/* Channel Sequence Register 1 */
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#define AT91_SAMA5D2_SEQR1 0x08
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/* Channel Sequence Register 2 */
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#define AT91_SAMA5D2_SEQR2 0x0c
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/* Channel Enable Register */
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#define AT91_SAMA5D2_CHER 0x10
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/* Channel Disable Register */
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#define AT91_SAMA5D2_CHDR 0x14
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/* Channel Status Register */
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#define AT91_SAMA5D2_CHSR 0x18
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/* Last Converted Data Register */
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#define AT91_SAMA5D2_LCDR 0x20
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/* Interrupt Enable Register */
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#define AT91_SAMA5D2_IER 0x24
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/* Interrupt Disable Register */
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#define AT91_SAMA5D2_IDR 0x28
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/* Interrupt Mask Register */
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#define AT91_SAMA5D2_IMR 0x2c
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/* Interrupt Status Register */
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#define AT91_SAMA5D2_ISR 0x30
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/* Last Channel Trigger Mode Register */
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#define AT91_SAMA5D2_LCTMR 0x34
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/* Last Channel Compare Window Register */
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#define AT91_SAMA5D2_LCCWR 0x38
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/* Overrun Status Register */
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#define AT91_SAMA5D2_OVER 0x3c
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/* Extended Mode Register */
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#define AT91_SAMA5D2_EMR 0x40
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/* Compare Window Register */
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#define AT91_SAMA5D2_CWR 0x44
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/* Channel Gain Register */
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#define AT91_SAMA5D2_CGR 0x48
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/* Channel Offset Register */
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#define AT91_SAMA5D2_COR 0x4c
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/* Channel Data Register 0 */
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#define AT91_SAMA5D2_CDR0 0x50
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/* Analog Control Register */
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#define AT91_SAMA5D2_ACR 0x94
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/* Touchscreen Mode Register */
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#define AT91_SAMA5D2_TSMR 0xb0
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/* Touchscreen X Position Register */
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#define AT91_SAMA5D2_XPOSR 0xb4
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/* Touchscreen Y Position Register */
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#define AT91_SAMA5D2_YPOSR 0xb8
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/* Touchscreen Pressure Register */
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#define AT91_SAMA5D2_PRESSR 0xbc
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/* Trigger Register */
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#define AT91_SAMA5D2_TRGR 0xc0
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/* Correction Select Register */
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#define AT91_SAMA5D2_COSR 0xd0
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/* Correction Value Register */
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#define AT91_SAMA5D2_CVR 0xd4
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/* Channel Error Correction Register */
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#define AT91_SAMA5D2_CECR 0xd8
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/* Write Protection Mode Register */
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#define AT91_SAMA5D2_WPMR 0xe4
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/* Write Protection Status Register */
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#define AT91_SAMA5D2_WPSR 0xe8
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/* Version Register */
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#define AT91_SAMA5D2_VERSION 0xfc
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#define AT91_AT91_SAMA5D2_CHAN(num, addr) \
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{ \
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.type = IIO_VOLTAGE, \
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.channel = num, \
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.address = addr, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = 12, \
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}, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
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.datasheet_name = "CH"#num, \
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.indexed = 1, \
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}
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#define at91_adc_readl(st, reg) readl_relaxed(st->base + reg)
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#define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg)
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struct at91_adc_soc_info {
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unsigned startup_time;
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unsigned min_sample_rate;
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unsigned max_sample_rate;
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};
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struct at91_adc_state {
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void __iomem *base;
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int irq;
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struct clk *per_clk;
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struct regulator *reg;
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struct regulator *vref;
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int vref_uv;
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const struct iio_chan_spec *chan;
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bool conversion_done;
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u32 conversion_value;
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struct at91_adc_soc_info soc_info;
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wait_queue_head_t wq_data_available;
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/*
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* lock to prevent concurrent 'single conversion' requests through
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* sysfs.
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*/
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struct mutex lock;
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};
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static const struct iio_chan_spec at91_adc_channels[] = {
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AT91_AT91_SAMA5D2_CHAN(0, 0x50),
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AT91_AT91_SAMA5D2_CHAN(1, 0x54),
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AT91_AT91_SAMA5D2_CHAN(2, 0x58),
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AT91_AT91_SAMA5D2_CHAN(3, 0x5c),
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AT91_AT91_SAMA5D2_CHAN(4, 0x60),
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AT91_AT91_SAMA5D2_CHAN(5, 0x64),
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AT91_AT91_SAMA5D2_CHAN(6, 0x68),
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AT91_AT91_SAMA5D2_CHAN(7, 0x6c),
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AT91_AT91_SAMA5D2_CHAN(8, 0x70),
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AT91_AT91_SAMA5D2_CHAN(9, 0x74),
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AT91_AT91_SAMA5D2_CHAN(10, 0x78),
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AT91_AT91_SAMA5D2_CHAN(11, 0x7c),
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};
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static unsigned at91_adc_startup_time(unsigned startup_time_min,
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unsigned adc_clk_khz)
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{
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const unsigned startup_lookup[] = {
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0, 8, 16, 24,
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64, 80, 96, 112,
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512, 576, 640, 704,
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768, 832, 896, 960
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};
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unsigned ticks_min, i;
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/*
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* Since the adc frequency is checked before, there is no reason
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* to not meet the startup time constraint.
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*/
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ticks_min = startup_time_min * adc_clk_khz / 1000;
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for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
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if (startup_lookup[i] > ticks_min)
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break;
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return i;
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}
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static void at91_adc_setup_samp_freq(struct at91_adc_state *st, unsigned freq)
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{
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struct iio_dev *indio_dev = iio_priv_to_dev(st);
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unsigned f_per, prescal, startup;
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f_per = clk_get_rate(st->per_clk);
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prescal = (f_per / (2 * freq)) - 1;
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startup = at91_adc_startup_time(st->soc_info.startup_time,
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freq / 1000);
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at91_adc_writel(st, AT91_SAMA5D2_MR,
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AT91_SAMA5D2_MR_TRANSFER(2)
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| AT91_SAMA5D2_MR_STARTUP(startup)
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| AT91_SAMA5D2_MR_PRESCAL(prescal));
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dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
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freq, startup, prescal);
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}
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static unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
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{
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unsigned f_adc, f_per = clk_get_rate(st->per_clk);
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unsigned mr, prescal;
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mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
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prescal = (mr >> AT91_SAMA5D2_MR_PRESCAL_OFFSET)
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& AT91_SAMA5D2_MR_PRESCAL_MAX;
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f_adc = f_per / (2 * (prescal + 1));
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return f_adc;
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}
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static irqreturn_t at91_adc_interrupt(int irq, void *private)
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{
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struct iio_dev *indio = private;
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struct at91_adc_state *st = iio_priv(indio);
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u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
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u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
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if (status & imr) {
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st->conversion_value = at91_adc_readl(st, st->chan->address);
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st->conversion_done = true;
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wake_up_interruptible(&st->wq_data_available);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int at91_adc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct at91_adc_state *st = iio_priv(indio_dev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&st->lock);
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st->chan = chan;
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at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
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at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));
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at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
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ret = wait_event_interruptible_timeout(st->wq_data_available,
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st->conversion_done,
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msecs_to_jiffies(1000));
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if (ret == 0)
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ret = -ETIMEDOUT;
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if (ret > 0) {
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*val = st->conversion_value;
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ret = IIO_VAL_INT;
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st->conversion_done = false;
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}
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at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));
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at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
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mutex_unlock(&st->lock);
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return ret;
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case IIO_CHAN_INFO_SCALE:
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*val = st->vref_uv / 1000;
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*val2 = chan->scan_type.realbits;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_SAMP_FREQ:
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*val = at91_adc_get_sample_freq(st);
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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}
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static int at91_adc_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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struct at91_adc_state *st = iio_priv(indio_dev);
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if (mask != IIO_CHAN_INFO_SAMP_FREQ)
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return -EINVAL;
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if (val < st->soc_info.min_sample_rate ||
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val > st->soc_info.max_sample_rate)
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return -EINVAL;
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at91_adc_setup_samp_freq(st, val);
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return 0;
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}
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static const struct iio_info at91_adc_info = {
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.read_raw = &at91_adc_read_raw,
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.write_raw = &at91_adc_write_raw,
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.driver_module = THIS_MODULE,
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};
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static int at91_adc_probe(struct platform_device *pdev)
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{
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struct iio_dev *indio_dev;
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struct at91_adc_state *st;
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struct resource *res;
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int ret;
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indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
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if (!indio_dev)
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return -ENOMEM;
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indio_dev->dev.parent = &pdev->dev;
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indio_dev->name = dev_name(&pdev->dev);
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->info = &at91_adc_info;
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indio_dev->channels = at91_adc_channels;
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indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels);
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st = iio_priv(indio_dev);
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ret = of_property_read_u32(pdev->dev.of_node,
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"atmel,min-sample-rate-hz",
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&st->soc_info.min_sample_rate);
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if (ret) {
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dev_err(&pdev->dev,
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"invalid or missing value for atmel,min-sample-rate-hz\n");
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return ret;
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}
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ret = of_property_read_u32(pdev->dev.of_node,
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"atmel,max-sample-rate-hz",
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&st->soc_info.max_sample_rate);
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if (ret) {
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dev_err(&pdev->dev,
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"invalid or missing value for atmel,max-sample-rate-hz\n");
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return ret;
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}
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|
|
|
ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
|
|
&st->soc_info.startup_time);
|
|
if (ret) {
|
|
dev_err(&pdev->dev,
|
|
"invalid or missing value for atmel,startup-time-ms\n");
|
|
return ret;
|
|
}
|
|
|
|
init_waitqueue_head(&st->wq_data_available);
|
|
mutex_init(&st->lock);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -EINVAL;
|
|
|
|
st->base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(st->base))
|
|
return PTR_ERR(st->base);
|
|
|
|
st->irq = platform_get_irq(pdev, 0);
|
|
if (st->irq <= 0) {
|
|
if (!st->irq)
|
|
st->irq = -ENXIO;
|
|
|
|
return st->irq;
|
|
}
|
|
|
|
st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
|
|
if (IS_ERR(st->per_clk))
|
|
return PTR_ERR(st->per_clk);
|
|
|
|
st->reg = devm_regulator_get(&pdev->dev, "vddana");
|
|
if (IS_ERR(st->reg))
|
|
return PTR_ERR(st->reg);
|
|
|
|
st->vref = devm_regulator_get(&pdev->dev, "vref");
|
|
if (IS_ERR(st->vref))
|
|
return PTR_ERR(st->vref);
|
|
|
|
ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
|
|
pdev->dev.driver->name, indio_dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = regulator_enable(st->reg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = regulator_enable(st->vref);
|
|
if (ret)
|
|
goto reg_disable;
|
|
|
|
st->vref_uv = regulator_get_voltage(st->vref);
|
|
if (st->vref_uv <= 0) {
|
|
ret = -EINVAL;
|
|
goto vref_disable;
|
|
}
|
|
|
|
at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
|
|
at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);
|
|
|
|
at91_adc_setup_samp_freq(st, st->soc_info.min_sample_rate);
|
|
|
|
ret = clk_prepare_enable(st->per_clk);
|
|
if (ret)
|
|
goto vref_disable;
|
|
|
|
platform_set_drvdata(pdev, indio_dev);
|
|
|
|
ret = iio_device_register(indio_dev);
|
|
if (ret < 0)
|
|
goto per_clk_disable_unprepare;
|
|
|
|
dev_info(&pdev->dev, "version: %x\n",
|
|
readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
|
|
|
|
return 0;
|
|
|
|
per_clk_disable_unprepare:
|
|
clk_disable_unprepare(st->per_clk);
|
|
vref_disable:
|
|
regulator_disable(st->vref);
|
|
reg_disable:
|
|
regulator_disable(st->reg);
|
|
return ret;
|
|
}
|
|
|
|
static int at91_adc_remove(struct platform_device *pdev)
|
|
{
|
|
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
|
|
struct at91_adc_state *st = iio_priv(indio_dev);
|
|
|
|
iio_device_unregister(indio_dev);
|
|
|
|
clk_disable_unprepare(st->per_clk);
|
|
|
|
regulator_disable(st->vref);
|
|
regulator_disable(st->reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id at91_adc_dt_match[] = {
|
|
{
|
|
.compatible = "atmel,sama5d2-adc",
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
|
|
|
|
static struct platform_driver at91_adc_driver = {
|
|
.probe = at91_adc_probe,
|
|
.remove = at91_adc_remove,
|
|
.driver = {
|
|
.name = "at91-sama5d2_adc",
|
|
.of_match_table = at91_adc_dt_match,
|
|
},
|
|
};
|
|
module_platform_driver(at91_adc_driver)
|
|
|
|
MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
|
|
MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
|
|
MODULE_LICENSE("GPL v2");
|