forked from Minki/linux
ed6e6a3487
The kernel queue module enables the amdkfd to establish kernel queues, not exposed to user space. The kernel queues are used for HIQ (HSA Interface Queue) and DIQ (Debug Interface Queue) operations v3: Removed use of internal typedefs and added use of the new gart allocation functions v4: Fixed a miscalculation in kernel queue wrapping v5: Move amdkfd from drm/radeon/ to drm/amd/ Change format of mqd structure to match latest KV firmware Add support for AQL queues creation to enable working with open-source HSA runtime Add define for kernel queue size Various fixes Signed-off-by: Ben Goz <ben.goz@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
406 lines
9.1 KiB
C
406 lines
9.1 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef KFD_PM4_HEADERS_H_
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#define KFD_PM4_HEADERS_H_
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#ifndef PM4_MES_HEADER_DEFINED
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#define PM4_MES_HEADER_DEFINED
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union PM4_MES_TYPE_3_HEADER {
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struct {
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uint32_t reserved1:8; /* < reserved */
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uint32_t opcode:8; /* < IT opcode */
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uint32_t count:14; /* < number of DWORDs - 1
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* in the information body.
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*/
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uint32_t type:2; /* < packet identifier.
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* It should be 3 for type 3 packets
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*/
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};
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uint32_t u32all;
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};
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#endif /* PM4_MES_HEADER_DEFINED */
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/* --------------------MES_SET_RESOURCES-------------------- */
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#ifndef PM4_MES_SET_RESOURCES_DEFINED
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#define PM4_MES_SET_RESOURCES_DEFINED
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enum set_resources_queue_type_enum {
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queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
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queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
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queue_type__mes_set_resources__hsa_debug_interface_queue = 4
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};
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struct pm4_set_resources {
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union {
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union PM4_MES_TYPE_3_HEADER header; /* header */
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uint32_t ordinal1;
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};
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union {
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struct {
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uint32_t vmid_mask:16;
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uint32_t unmap_latency:8;
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uint32_t reserved1:5;
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enum set_resources_queue_type_enum queue_type:3;
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} bitfields2;
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uint32_t ordinal2;
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};
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uint32_t queue_mask_lo;
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uint32_t queue_mask_hi;
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uint32_t gws_mask_lo;
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uint32_t gws_mask_hi;
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union {
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struct {
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uint32_t oac_mask:16;
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uint32_t reserved2:16;
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} bitfields7;
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uint32_t ordinal7;
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};
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union {
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struct {
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uint32_t gds_heap_base:6;
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uint32_t reserved3:5;
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uint32_t gds_heap_size:6;
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uint32_t reserved4:15;
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} bitfields8;
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uint32_t ordinal8;
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};
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};
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#endif
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/*--------------------MES_RUN_LIST-------------------- */
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#ifndef PM4_MES_RUN_LIST_DEFINED
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#define PM4_MES_RUN_LIST_DEFINED
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struct pm4_runlist {
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union {
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union PM4_MES_TYPE_3_HEADER header; /* header */
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uint32_t ordinal1;
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};
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union {
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struct {
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uint32_t reserved1:2;
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uint32_t ib_base_lo:30;
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} bitfields2;
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uint32_t ordinal2;
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};
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union {
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struct {
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uint32_t ib_base_hi:16;
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uint32_t reserved2:16;
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} bitfields3;
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uint32_t ordinal3;
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};
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union {
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struct {
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uint32_t ib_size:20;
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uint32_t chain:1;
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uint32_t offload_polling:1;
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uint32_t reserved3:1;
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uint32_t valid:1;
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uint32_t reserved4:8;
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} bitfields4;
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uint32_t ordinal4;
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};
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};
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#endif
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/*--------------------MES_MAP_PROCESS-------------------- */
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#ifndef PM4_MES_MAP_PROCESS_DEFINED
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#define PM4_MES_MAP_PROCESS_DEFINED
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struct pm4_map_process {
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union {
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union PM4_MES_TYPE_3_HEADER header; /* header */
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uint32_t ordinal1;
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};
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union {
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struct {
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uint32_t pasid:16;
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uint32_t reserved1:8;
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uint32_t diq_enable:1;
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uint32_t process_quantum:7;
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} bitfields2;
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uint32_t ordinal2;
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};
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union {
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struct {
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uint32_t page_table_base:28;
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uint32_t reserved3:4;
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} bitfields3;
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uint32_t ordinal3;
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};
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uint32_t sh_mem_bases;
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uint32_t sh_mem_ape1_base;
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uint32_t sh_mem_ape1_limit;
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uint32_t sh_mem_config;
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uint32_t gds_addr_lo;
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uint32_t gds_addr_hi;
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union {
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struct {
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uint32_t num_gws:6;
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uint32_t reserved4:2;
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uint32_t num_oac:4;
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uint32_t reserved5:4;
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uint32_t gds_size:6;
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uint32_t num_queues:10;
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} bitfields10;
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uint32_t ordinal10;
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};
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};
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#endif
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/*--------------------MES_MAP_QUEUES--------------------*/
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#ifndef PM4_MES_MAP_QUEUES_DEFINED
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#define PM4_MES_MAP_QUEUES_DEFINED
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enum map_queues_queue_sel_enum {
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queue_sel__mes_map_queues__map_to_specified_queue_slots = 0,
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queue_sel__mes_map_queues__map_to_hws_determined_queue_slots = 1,
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queue_sel__mes_map_queues__enable_process_queues = 2
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};
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enum map_queues_vidmem_enum {
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vidmem__mes_map_queues__uses_no_video_memory = 0,
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vidmem__mes_map_queues__uses_video_memory = 1
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};
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enum map_queues_alloc_format_enum {
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alloc_format__mes_map_queues__one_per_pipe = 0,
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alloc_format__mes_map_queues__all_on_one_pipe = 1
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};
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enum map_queues_engine_sel_enum {
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engine_sel__mes_map_queues__compute = 0,
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engine_sel__mes_map_queues__sdma0 = 2,
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engine_sel__mes_map_queues__sdma1 = 3
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};
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struct pm4_map_queues {
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union {
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union PM4_MES_TYPE_3_HEADER header; /* header */
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uint32_t ordinal1;
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};
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union {
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struct {
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uint32_t reserved1:4;
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enum map_queues_queue_sel_enum queue_sel:2;
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uint32_t reserved2:2;
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uint32_t vmid:4;
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uint32_t reserved3:4;
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enum map_queues_vidmem_enum vidmem:2;
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uint32_t reserved4:6;
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enum map_queues_alloc_format_enum alloc_format:2;
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enum map_queues_engine_sel_enum engine_sel:3;
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uint32_t num_queues:3;
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} bitfields2;
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uint32_t ordinal2;
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};
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struct {
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union {
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struct {
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uint32_t reserved5:2;
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uint32_t doorbell_offset:21;
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uint32_t reserved6:3;
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uint32_t queue:6;
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} bitfields3;
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uint32_t ordinal3;
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};
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uint32_t mqd_addr_lo;
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uint32_t mqd_addr_hi;
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uint32_t wptr_addr_lo;
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uint32_t wptr_addr_hi;
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} mes_map_queues_ordinals[1]; /* 1..N of these ordinal groups */
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};
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#endif
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/*--------------------MES_QUERY_STATUS--------------------*/
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#ifndef PM4_MES_QUERY_STATUS_DEFINED
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#define PM4_MES_QUERY_STATUS_DEFINED
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enum query_status_interrupt_sel_enum {
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interrupt_sel__mes_query_status__completion_status = 0,
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interrupt_sel__mes_query_status__process_status = 1,
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interrupt_sel__mes_query_status__queue_status = 2
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};
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enum query_status_command_enum {
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command__mes_query_status__interrupt_only = 0,
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command__mes_query_status__fence_only_immediate = 1,
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command__mes_query_status__fence_only_after_write_ack = 2,
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command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
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};
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enum query_status_engine_sel_enum {
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engine_sel__mes_query_status__compute = 0,
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engine_sel__mes_query_status__sdma0_queue = 2,
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engine_sel__mes_query_status__sdma1_queue = 3
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};
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struct pm4_query_status {
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union {
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union PM4_MES_TYPE_3_HEADER header; /* header */
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uint32_t ordinal1;
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};
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union {
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struct {
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uint32_t context_id:28;
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enum query_status_interrupt_sel_enum interrupt_sel:2;
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enum query_status_command_enum command:2;
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} bitfields2;
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uint32_t ordinal2;
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};
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union {
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struct {
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uint32_t pasid:16;
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uint32_t reserved1:16;
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} bitfields3a;
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struct {
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uint32_t reserved2:2;
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uint32_t doorbell_offset:21;
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uint32_t reserved3:3;
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enum query_status_engine_sel_enum engine_sel:3;
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uint32_t reserved4:3;
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} bitfields3b;
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uint32_t ordinal3;
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};
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uint32_t addr_lo;
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uint32_t addr_hi;
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uint32_t data_lo;
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uint32_t data_hi;
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};
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#endif
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/*--------------------MES_UNMAP_QUEUES--------------------*/
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#ifndef PM4_MES_UNMAP_QUEUES_DEFINED
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#define PM4_MES_UNMAP_QUEUES_DEFINED
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enum unmap_queues_action_enum {
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action__mes_unmap_queues__preempt_queues = 0,
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action__mes_unmap_queues__reset_queues = 1,
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action__mes_unmap_queues__disable_process_queues = 2
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};
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enum unmap_queues_queue_sel_enum {
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queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
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queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
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queue_sel__mes_unmap_queues__perform_request_on_all_active_queues = 2
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};
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enum unmap_queues_engine_sel_enum {
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engine_sel__mes_unmap_queues__compute = 0,
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engine_sel__mes_unmap_queues__sdma0 = 2,
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engine_sel__mes_unmap_queues__sdma1 = 3
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};
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struct pm4_unmap_queues {
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union {
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union PM4_MES_TYPE_3_HEADER header; /* header */
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uint32_t ordinal1;
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};
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union {
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struct {
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enum unmap_queues_action_enum action:2;
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uint32_t reserved1:2;
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enum unmap_queues_queue_sel_enum queue_sel:2;
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uint32_t reserved2:20;
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enum unmap_queues_engine_sel_enum engine_sel:3;
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uint32_t num_queues:3;
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} bitfields2;
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uint32_t ordinal2;
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};
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union {
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struct {
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uint32_t pasid:16;
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uint32_t reserved3:16;
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} bitfields3a;
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struct {
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uint32_t reserved4:2;
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uint32_t doorbell_offset0:21;
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uint32_t reserved5:9;
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} bitfields3b;
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uint32_t ordinal3;
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};
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union {
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struct {
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uint32_t reserved6:2;
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uint32_t doorbell_offset1:21;
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uint32_t reserved7:9;
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} bitfields4;
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uint32_t ordinal4;
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};
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union {
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struct {
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uint32_t reserved8:2;
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uint32_t doorbell_offset2:21;
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uint32_t reserved9:9;
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} bitfields5;
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uint32_t ordinal5;
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};
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union {
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struct {
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uint32_t reserved10:2;
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uint32_t doorbell_offset3:21;
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uint32_t reserved11:9;
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} bitfields6;
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uint32_t ordinal6;
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};
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};
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#endif
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enum {
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CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
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};
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#endif /* KFD_PM4_HEADERS_H_ */
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