Kees Cook 8dbec27a24 x86/asm: Pin sensitive CR0 bits ... With sensitive CR4 bits pinned now, it's possible that the WP bit for CR0 might become a target as well. Following the same reasoning for the CR4 pinning, pin CR0's WP bit. Contrary to the cpu feature dependend CR4 pinning this can be done with a constant value. Suggested-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Dave Hansen <dave.hansen@intel.com> Cc: kernel-hardening@lists.openwall.com Link: https://lkml.kernel.org/r/20190618045503.39105-4-keescook@chromium.org		2019-06-22 11:55:22 +02:00
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asm	x86/asm: Pin sensitive CR0 bits	2019-06-22 11:55:22 +02:00
uapi/asm	treewide: Add SPDX license identifier - Kbuild	2019-05-30 11:32:33 -07:00