Guo Ren 8d11f21a73 csky: Fixup barrier design ... Remove shareable bit for ordering barrier, just keep ordering in current hart is enough for SMP. Using three continuous sync.is as PTW barrier to prevent speculative PTW in 860 microarchitecture. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>		2021-01-12 09:52:40 +08:00
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asm	csky: Fixup barrier design	2021-01-12 09:52:40 +08:00
uapi/asm	csky: Fixup compile warning for three unimplemented syscalls	2020-02-21 15:43:25 +08:00