ce0d60f731
Previously, the mips_machtype variable was always initialized to MACH_INGENIC_JZ4740 even if running on different SoCs. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18486/ Signed-off-by: James Hogan <jhogan@kernel.org>
104 lines
2.3 KiB
C
104 lines
2.3 KiB
C
/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* Copyright (C) 2011, Maarten ter Huurne <maarten@treewalker.org>
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* JZ4740 setup code
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/kernel.h>
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#include <linux/libfdt.h>
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#include <linux/of_fdt.h>
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#include <asm/bootinfo.h>
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#include <asm/prom.h>
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#include <asm/mach-jz4740/base.h>
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#include "reset.h"
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#define JZ4740_EMC_SDRAM_CTRL 0x80
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static void __init jz4740_detect_mem(void)
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{
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void __iomem *jz_emc_base;
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u32 ctrl, bus, bank, rows, cols;
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phys_addr_t size;
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jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100);
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ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL);
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bus = 2 - ((ctrl >> 31) & 1);
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bank = 1 + ((ctrl >> 19) & 1);
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cols = 8 + ((ctrl >> 26) & 7);
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rows = 11 + ((ctrl >> 20) & 3);
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printk(KERN_DEBUG
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"SDRAM preconfigured: bus:%u bank:%u rows:%u cols:%u\n",
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bus, bank, rows, cols);
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iounmap(jz_emc_base);
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size = 1 << (bus + bank + cols + rows);
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add_memory_region(0, size, BOOT_MEM_RAM);
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}
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static unsigned long __init get_board_mach_type(const void *fdt)
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{
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if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4780"))
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return MACH_INGENIC_JZ4780;
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if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4770"))
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return MACH_INGENIC_JZ4770;
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return MACH_INGENIC_JZ4740;
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}
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void __init plat_mem_setup(void)
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{
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int offset;
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jz4740_reset_init();
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__dt_setup_arch(__dtb_start);
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offset = fdt_path_offset(__dtb_start, "/memory");
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if (offset < 0)
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jz4740_detect_mem();
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mips_machtype = get_board_mach_type(__dtb_start);
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}
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void __init device_tree_init(void)
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{
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if (!initial_boot_params)
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return;
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unflatten_and_copy_device_tree();
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}
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const char *get_system_type(void)
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{
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switch (mips_machtype) {
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case MACH_INGENIC_JZ4780:
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return "JZ4780";
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case MACH_INGENIC_JZ4770:
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return "JZ4770";
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default:
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return "JZ4740";
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}
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}
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void __init arch_init_irq(void)
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{
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irqchip_init();
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}
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