forked from Minki/linux
8ca1ca8f60
The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com> |
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| .. | ||
| clk-cpu.c | ||
| clk-inverter.c | ||
| clk-mmc-phase.c | ||
| clk-pll.c | ||
| clk-rk3036.c | ||
| clk-rk3188.c | ||
| clk-rk3288.c | ||
| clk-rk3368.c | ||
| clk-rockchip.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||
| softrst.c | ||