forked from Minki/linux
a1467faa10
Starting with commit6b2117ad65
("of: property: fw_devlink: Add support for "resets" and "pwms""), the imx-drm driver fails to load due to forever dormant devlinks to the reset-controller node. This node was never associated with a struct device. Add a platform device to allow fw_devnode to activate the devlinks. Fixes:6b2117ad65
("of: property: fw_devlink: Add support for "resets" and "pwms"") Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Saravana Kannan <saravanak@google.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
239 lines
5.8 KiB
C
239 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/smp.h>
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#include <asm/smp_plat.h>
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#include "common.h"
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#include "hardware.h"
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#define SRC_SCR 0x000
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#define SRC_GPR1_V1 0x020
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#define SRC_GPR1_V2 0x074
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#define SRC_GPR1(gpr_v2) ((gpr_v2) ? SRC_GPR1_V2 : SRC_GPR1_V1)
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#define BP_SRC_SCR_WARM_RESET_ENABLE 0
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#define BP_SRC_SCR_SW_GPU_RST 1
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#define BP_SRC_SCR_SW_VPU_RST 2
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#define BP_SRC_SCR_SW_IPU1_RST 3
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#define BP_SRC_SCR_SW_OPEN_VG_RST 4
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#define BP_SRC_SCR_SW_IPU2_RST 12
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#define BP_SRC_SCR_CORE1_RST 14
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#define BP_SRC_SCR_CORE1_ENABLE 22
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/* below is for i.MX7D */
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#define SRC_A7RCR1 0x008
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#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
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#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
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#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
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#define GPC_PGC_C1 0x840
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#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
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static void __iomem *src_base;
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static DEFINE_SPINLOCK(scr_lock);
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static bool gpr_v2;
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static void __iomem *gpc_base;
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static const int sw_reset_bits[5] = {
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BP_SRC_SCR_SW_GPU_RST,
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BP_SRC_SCR_SW_VPU_RST,
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BP_SRC_SCR_SW_IPU1_RST,
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BP_SRC_SCR_SW_OPEN_VG_RST,
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BP_SRC_SCR_SW_IPU2_RST
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};
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static int imx_src_reset_module(struct reset_controller_dev *rcdev,
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unsigned long sw_reset_idx)
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{
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unsigned long timeout;
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unsigned long flags;
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int bit;
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u32 val;
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if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits))
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return -EINVAL;
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bit = 1 << sw_reset_bits[sw_reset_idx];
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spin_lock_irqsave(&scr_lock, flags);
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val = readl_relaxed(src_base + SRC_SCR);
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val |= bit;
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writel_relaxed(val, src_base + SRC_SCR);
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spin_unlock_irqrestore(&scr_lock, flags);
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timeout = jiffies + msecs_to_jiffies(1000);
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while (readl(src_base + SRC_SCR) & bit) {
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if (time_after(jiffies, timeout))
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return -ETIME;
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cpu_relax();
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}
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return 0;
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}
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static const struct reset_control_ops imx_src_ops = {
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.reset = imx_src_reset_module,
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};
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static void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
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{
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writel_relaxed(enable, gpc_base + offset);
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}
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/*
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* The motivation for bringing up the second i.MX7D core inside the kernel
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* is that legacy vendor bootloaders usually do not implement PSCI support.
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* This is a significant blocker for systems in the field that are running old
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* bootloader versions to upgrade to a modern mainline kernel version, as only
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* one CPU of the i.MX7D would be brought up.
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* Bring up the second i.MX7D core inside the kernel to make the migration
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* path to mainline kernel easier for the existing iMX7D users.
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*/
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void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn)
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{
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u32 reg = pdn ? GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ;
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u32 val, pup;
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int ret;
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imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
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val = readl_relaxed(gpc_base + reg);
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val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
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writel_relaxed(val, gpc_base + reg);
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ret = readl_relaxed_poll_timeout_atomic(gpc_base + reg, pup,
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!(pup & BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7),
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5, 1000000);
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if (ret < 0) {
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pr_err("i.MX7D: CORE1_A7 power up timeout\n");
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val &= ~BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
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writel_relaxed(val, gpc_base + reg);
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}
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imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
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}
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void imx_enable_cpu(int cpu, bool enable)
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{
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u32 mask, val;
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cpu = cpu_logical_map(cpu);
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spin_lock(&scr_lock);
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if (gpr_v2) {
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if (enable)
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imx_gpcv2_set_core1_pdn_pup_by_software(false);
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mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
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val = readl_relaxed(src_base + SRC_A7RCR1);
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val = enable ? val | mask : val & ~mask;
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writel_relaxed(val, src_base + SRC_A7RCR1);
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} else {
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mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
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val = readl_relaxed(src_base + SRC_SCR);
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val = enable ? val | mask : val & ~mask;
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val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
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writel_relaxed(val, src_base + SRC_SCR);
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}
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spin_unlock(&scr_lock);
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}
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void imx_set_cpu_jump(int cpu, void *jump_addr)
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{
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cpu = cpu_logical_map(cpu);
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writel_relaxed(__pa_symbol(jump_addr),
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src_base + SRC_GPR1(gpr_v2) + cpu * 8);
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}
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u32 imx_get_cpu_arg(int cpu)
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{
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cpu = cpu_logical_map(cpu);
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return readl_relaxed(src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4);
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}
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void imx_set_cpu_arg(int cpu, u32 arg)
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{
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cpu = cpu_logical_map(cpu);
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writel_relaxed(arg, src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4);
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}
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void __init imx_src_init(void)
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{
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struct device_node *np;
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u32 val;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
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if (!np)
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return;
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src_base = of_iomap(np, 0);
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WARN_ON(!src_base);
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/*
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* force warm reset sources to generate cold reset
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* for a more reliable restart
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*/
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spin_lock(&scr_lock);
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val = readl_relaxed(src_base + SRC_SCR);
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val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
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writel_relaxed(val, src_base + SRC_SCR);
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spin_unlock(&scr_lock);
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}
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void __init imx7_src_init(void)
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{
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struct device_node *np;
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gpr_v2 = true;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-src");
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if (!np)
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return;
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src_base = of_iomap(np, 0);
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if (!src_base)
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return;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpc");
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if (!np)
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return;
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gpc_base = of_iomap(np, 0);
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if (!gpc_base)
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return;
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}
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static const struct of_device_id imx_src_dt_ids[] = {
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{ .compatible = "fsl,imx51-src" },
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{ /* sentinel */ }
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};
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static int imx_src_probe(struct platform_device *pdev)
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{
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struct reset_controller_dev *rcdev;
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rcdev = devm_kzalloc(&pdev->dev, sizeof(*rcdev), GFP_KERNEL);
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if (!rcdev)
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return -ENOMEM;
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rcdev->ops = &imx_src_ops;
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rcdev->dev = &pdev->dev;
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rcdev->of_node = pdev->dev.of_node;
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rcdev->nr_resets = ARRAY_SIZE(sw_reset_bits);
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return devm_reset_controller_register(&pdev->dev, rcdev);
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}
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static struct platform_driver imx_src_driver = {
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.driver = {
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.name = "imx-src",
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.of_match_table = imx_src_dt_ids,
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},
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.probe = imx_src_probe,
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};
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builtin_platform_driver(imx_src_driver);
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