linux/drivers/gpu/drm/amd/display/amdgpu_dm
David Francis 8c20a1ed9b drm/amd/display: MST DSC compute fair share
If there is limited link bandwidth on a MST network,
it must be divided fairly between the streams on that network

Implement an algorithm to determine the correct DSC config
for each stream

The algorithm:
This
     [                   ]          ( )
represents the range of bandwidths possible for a given stream.
The [] area represents the range of DSC configs, and the ()
represents no DSC. The bandwidth used increases from left to right.

First, try disabling DSC on all streams
     [                  ]          (|)
     [                     ]            (|)
Check this against the bandwidth limits of the link and each branch
(including each endpoint). If it passes, the job is done

Second, try maximum DSC compression on all streams
that support DSC
     [|         ]        ( )
     [|                ]         ( )
If this does not pass, then enabling this combination of streams
is impossible

Otherwise, divide the remaining bandwidth evenly amongst the streams
     [        |  ]         ( )
     [        |      ]        ( )

If one or more of the streams reach minimum compression, evenly
divide the reamining bandwidth amongst the remaining streams
     [    |] ( )
     [       |]   ( )
     [                 |   ]               ( )
     [                 |      ]                  ( )

If all streams can reach minimum compression, disable compression
greedily
     [      |]  ( )
     [        |]    ( )
     [                 ]                                (|)

Perform this algorithm on each full update, on each MST link
with at least one DSC stream on it

After the configs are computed, call
dcn20_add_dsc_to_stream_resource on each stream with DSC enabled.
It is only after all streams are created that we can know which
of them will need DSC.

Do all of this at the end of amdgpu atomic check.  If it fails,
fail check; This combination of timings cannot be supported.

v2: Use drm_dp_mst_atomic_check to validate bw for certain dsc
configurations

v3: Use dc_dsc_policy structure to get min and max bpp rate
for DSC configuration

Acked-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-09 18:07:47 -05:00
..
amdgpu_dm_color.c drm/amd/display: Free gamma after calculating legacy transfer function 2019-10-25 16:50:07 -04:00
amdgpu_dm_crc.c drm/amd/display: Added pixel dynamic expansion control. 2019-10-10 19:24:26 -05:00
amdgpu_dm_crc.h drm/amd/display: Split out DC programming for CRC capture 2019-08-21 22:18:25 -05:00
amdgpu_dm_debugfs.c drm/amd/display: add color space option when sending link test pattern 2019-11-19 10:12:52 -05:00
amdgpu_dm_debugfs.h amdgpu_dm: no need to check return value of debugfs_create functions 2019-06-13 13:59:49 -05:00
amdgpu_dm_hdcp.c drm/amd/display: Null check aconnector in event_property_validate 2019-11-26 14:50:38 -05:00
amdgpu_dm_hdcp.h drm/amd/display: add force Type0/1 flag 2019-11-19 10:12:53 -05:00
amdgpu_dm_helpers.c drm/amd/display: Write DSC enable to MST DPCD 2020-01-09 18:07:47 -05:00
amdgpu_dm_irq.c drm/amd: use list_for_each_entry for list iteration. 2020-01-07 12:04:16 -05:00
amdgpu_dm_irq.h
amdgpu_dm_mst_types.c drm/amd/display: MST DSC compute fair share 2020-01-09 18:07:47 -05:00
amdgpu_dm_mst_types.h drm/amd/display: MST DSC compute fair share 2020-01-09 18:07:47 -05:00
amdgpu_dm_pp_smu.c drm/amd/display: add default clocks if not able to fetch them 2019-11-26 12:19:08 -05:00
amdgpu_dm_services.c drm/amd: drop use of drmP.h in display/ 2019-06-10 23:00:20 +02:00
amdgpu_dm_trace.h drm/amd/display: Add tracing to dc 2018-12-05 17:49:49 -05:00
amdgpu_dm.c drm/amd/display: MST DSC compute fair share 2020-01-09 18:07:47 -05:00
amdgpu_dm.h drm/amd/display: Validate DSC caps on MST endpoints 2020-01-09 18:07:47 -05:00
Makefile drm/amd/display: Create amdgpu_dm_hdcp 2019-10-03 09:10:58 -05:00