Christoph Hellwig 3320648ecc riscv: cleanup the default power off implementation ...

Move the sbi poweroff to a separate function and file that is only
compiled if CONFIG_SBI is set.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
[paul.walmsley@sifive.com: split the WFI fix into a separate patch]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>

2019-11-13 13:22:52 -08:00

..

vdso

riscv: Fix perf record without libelf support

2019-07-31 12:26:10 -07:00

.gitignore

RISC-V: Build Infrastructure

2017-09-26 15:26:49 -07:00

asm-offsets.c

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

cacheinfo.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286

2019-06-05 17:36:37 +02:00

cpu.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286

2019-06-05 17:36:37 +02:00

cpufeature.c

riscv: add missing header file includes

2019-10-28 00:46:01 -07:00

entry.S

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

fpu.S

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

ftrace.c

riscv: add missing newlines to printk messages

2019-02-11 15:34:56 -08:00

head.h

riscv: add prototypes for assembly language functions from head.S

2019-10-28 00:46:00 -07:00

head.S

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

irq.c

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

Makefile

riscv: cleanup the default power off implementation

2019-11-13 13:22:52 -08:00

mcount-dyn.S

riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support

2018-04-02 19:59:13 -07:00

mcount.S

RISC-V: remove the unused return_to_handler export

2018-10-22 17:38:12 -07:00

module-sections.c

riscv: add missing header file includes

2019-10-28 00:46:01 -07:00

module.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30 11:26:37 -07:00

module.lds

RISC-V: Add section of GOT.PLT for kernel module

2018-04-02 20:00:54 -07:00

perf_callchain.c

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

perf_event.c

RISC-V: Access CSRs using CSR numbers

2019-05-16 20:42:11 -07:00

perf_regs.c

riscv: Add support for perf registers sampling

2019-09-05 00:48:58 -07:00

process.c

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

ptrace.c

riscv: for C functions called only from assembly, mark with __visible

2019-10-28 00:46:02 -07:00

reset.c

riscv: cleanup the default power off implementation

2019-11-13 13:22:52 -08:00

riscv_ksyms.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19 17:09:55 +02:00

sbi.c

riscv: cleanup the default power off implementation

2019-11-13 13:22:52 -08:00

setup.c

riscv: add prototypes for assembly language functions from head.S

2019-10-28 00:46:00 -07:00

signal.c

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

smp.c

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

smpboot.c

riscv: for C functions called only from assembly, mark with __visible

2019-10-28 00:46:02 -07:00

stacktrace.c

riscv: Add perf callchain support

2019-09-04 12:43:00 -07:00

sys_riscv.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286

2019-06-05 17:36:37 +02:00

syscall_table.c

riscv: add missing header file includes

2019-10-28 00:46:01 -07:00

time.c

riscv: add missing header file includes

2019-10-28 00:46:01 -07:00

traps.c

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

vdso.c

riscv: add missing header file includes

2019-10-28 00:46:01 -07:00

vmlinux.lds.S

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286

2019-06-05 17:36:37 +02:00