forked from Minki/linux
8b5869ad85
This fixes an error in the inline asm in try_lock_hpte() where we were erroneously using a register number as an immediate operand. The bug only affects an error path, and in fact the code will still work as long as the compiler chooses some register other than r0 for the "bits" variable. Nevertheless it should still be fixed. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
241 lines
6.1 KiB
C
241 lines
6.1 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright SUSE Linux Products GmbH 2010
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#ifndef __ASM_KVM_BOOK3S_64_H__
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#define __ASM_KVM_BOOK3S_64_H__
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#ifdef CONFIG_KVM_BOOK3S_PR
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static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
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{
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preempt_disable();
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return &get_paca()->shadow_vcpu;
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}
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static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
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{
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preempt_enable();
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}
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#endif
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#define SPAPR_TCE_SHIFT 12
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#ifdef CONFIG_KVM_BOOK3S_64_HV
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#define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */
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extern int kvm_hpt_order; /* order of preallocated HPTs */
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#endif
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#define VRMA_VSID 0x1ffffffUL /* 1TB VSID reserved for VRMA */
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/*
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* We use a lock bit in HPTE dword 0 to synchronize updates and
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* accesses to each HPTE, and another bit to indicate non-present
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* HPTEs.
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*/
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#define HPTE_V_HVLOCK 0x40UL
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#define HPTE_V_ABSENT 0x20UL
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static inline long try_lock_hpte(unsigned long *hpte, unsigned long bits)
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{
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unsigned long tmp, old;
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asm volatile(" ldarx %0,0,%2\n"
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" and. %1,%0,%3\n"
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" bne 2f\n"
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" ori %0,%0,%4\n"
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" stdcx. %0,0,%2\n"
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" beq+ 2f\n"
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" mr %1,%3\n"
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"2: isync"
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: "=&r" (tmp), "=&r" (old)
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: "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
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: "cc", "memory");
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return old == 0;
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}
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static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
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unsigned long pte_index)
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{
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unsigned long rb, va_low;
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rb = (v & ~0x7fUL) << 16; /* AVA field */
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va_low = pte_index >> 3;
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if (v & HPTE_V_SECONDARY)
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va_low = ~va_low;
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/* xor vsid from AVA */
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if (!(v & HPTE_V_1TB_SEG))
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va_low ^= v >> 12;
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else
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va_low ^= v >> 24;
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va_low &= 0x7ff;
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if (v & HPTE_V_LARGE) {
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rb |= 1; /* L field */
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if (cpu_has_feature(CPU_FTR_ARCH_206) &&
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(r & 0xff000)) {
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/* non-16MB large page, must be 64k */
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/* (masks depend on page size) */
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rb |= 0x1000; /* page encoding in LP field */
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rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
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rb |= (va_low & 0xfe); /* AVAL field (P7 doesn't seem to care) */
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}
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} else {
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/* 4kB page */
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rb |= (va_low & 0x7ff) << 12; /* remaining 11b of VA */
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}
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rb |= (v >> 54) & 0x300; /* B field */
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return rb;
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}
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static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
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{
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/* only handle 4k, 64k and 16M pages for now */
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if (!(h & HPTE_V_LARGE))
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return 1ul << 12; /* 4k page */
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if ((l & 0xf000) == 0x1000 && cpu_has_feature(CPU_FTR_ARCH_206))
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return 1ul << 16; /* 64k page */
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if ((l & 0xff000) == 0)
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return 1ul << 24; /* 16M page */
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return 0; /* error */
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}
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static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
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{
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return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
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}
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static inline int hpte_is_writable(unsigned long ptel)
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{
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unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP);
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return pp != PP_RXRX && pp != PP_RXXX;
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}
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static inline unsigned long hpte_make_readonly(unsigned long ptel)
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{
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if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX)
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ptel = (ptel & ~HPTE_R_PP) | PP_RXXX;
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else
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ptel |= PP_RXRX;
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return ptel;
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}
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static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
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{
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unsigned int wimg = ptel & HPTE_R_WIMG;
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/* Handle SAO */
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if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
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cpu_has_feature(CPU_FTR_ARCH_206))
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wimg = HPTE_R_M;
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if (!io_type)
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return wimg == HPTE_R_M;
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return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;
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}
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/*
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* Lock and read a linux PTE. If it's present and writable, atomically
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* set dirty and referenced bits and return the PTE, otherwise return 0.
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*/
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static inline pte_t kvmppc_read_update_linux_pte(pte_t *p, int writing)
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{
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pte_t pte, tmp;
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/* wait until _PAGE_BUSY is clear then set it atomically */
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__asm__ __volatile__ (
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"1: ldarx %0,0,%3\n"
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" andi. %1,%0,%4\n"
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" bne- 1b\n"
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" ori %1,%0,%4\n"
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" stdcx. %1,0,%3\n"
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" bne- 1b"
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: "=&r" (pte), "=&r" (tmp), "=m" (*p)
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: "r" (p), "i" (_PAGE_BUSY)
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: "cc");
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if (pte_present(pte)) {
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pte = pte_mkyoung(pte);
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if (writing && pte_write(pte))
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pte = pte_mkdirty(pte);
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}
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*p = pte; /* clears _PAGE_BUSY */
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return pte;
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}
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/* Return HPTE cache control bits corresponding to Linux pte bits */
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static inline unsigned long hpte_cache_bits(unsigned long pte_val)
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{
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#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
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return pte_val & (HPTE_R_W | HPTE_R_I);
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#else
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return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
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((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
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#endif
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}
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static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
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{
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if (key)
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return PP_RWRX <= pp && pp <= PP_RXRX;
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return 1;
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}
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static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
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{
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if (key)
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return pp == PP_RWRW;
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return pp <= PP_RWRW;
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}
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static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
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{
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unsigned long skey;
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skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
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((hpte_r & HPTE_R_KEY_LO) >> 9);
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return (amr >> (62 - 2 * skey)) & 3;
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}
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static inline void lock_rmap(unsigned long *rmap)
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{
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do {
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while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
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cpu_relax();
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} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
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}
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static inline void unlock_rmap(unsigned long *rmap)
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{
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__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
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}
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static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
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unsigned long pagesize)
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{
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unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
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if (pagesize <= PAGE_SIZE)
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return 1;
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return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
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}
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#endif /* __ASM_KVM_BOOK3S_64_H__ */
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